Your chip works perfectly in simulation. It passes DRC. It passes LVS. Then you tape out, and a fraction of the dies come back dead with random gate oxide failures. Welcome to the antenna effect, one of the strangest failure mechanisms in CMOS: transistors that were destroyed before the chip was even finished being built.

Here's the physics. Modern chips are fabricated layer by layer. After transistors are made in silicon, metal interconnects are added on top — Metal 1, then Metal 2, all the way up to Metal 10+ on modern processes. Each metal layer is patterned using plasma etching, which is essentially a bath of charged ions. Those ions don't care what they land on. They deposit charge onto every exposed metal surface.

If a piece of metal is floating during etch and connected only to a transistor gate, it acts as a tiny antenna, collecting charge that has nowhere to go. The voltage on the gate rises until the thin gate oxide (a few atoms thick in modern nodes) breaks down. Permanent damage. The transistor is now leaky, slow, or completely dead — and there's no way to detect it electrically until the chip is packaged.

The danger depends on the antenna ratio: the area of metal collecting charge divided by the gate oxide area it's connected to. A typical foundry rule:

• Antenna ratio = (metal area) / (gate area)
• Maximum allowed for Metal 1: often around 400:1
• Maximum cumulative across all metal layers: typically 2000:1 or less

So if a gate has 0.01 µm² of oxide, the routed Metal 1 wire connected to it can be at most ~4 µm² before you violate the rule.

Real-world example: Place-and-route tools route a long bus from the south side of a block to a flip-flop on the north side using only Metal 2. That single net might span 500 µm of metal connected to one small gate. Antenna violation. The fix is one of three tricks: (1) jog the wire up to higher metal then back down, breaking the antenna because the higher layer didn't exist during Metal 2 etch, (2) insert an antenna diode — a tiny reverse-biased diode to substrate that harmlessly bleeds off charge before it reaches the gate, or (3) split the net into shorter segments connected via vias to layers etched later.

Modern EDA tools fix antenna violations automatically during routing, usually by inserting diodes. Each diode costs area and a tiny bit of leakage, but it guarantees the transistor survives manufacturing. On a chip with 100 million nets, you might end up with hundreds of thousands of antenna diodes scattered throughout the design.