A single DRAM chip isn't one big array. It's split into banks — typically 8 banks per chip in DDR4, 16 in DDR5, and 32 "bank groups × banks" addressable units in modern parts. Each bank is an independent sub-array with its own row buffer, its own activated row, and its own state machine. This is the structural foundation of memory parallelism: while one bank is paying the 15ns cost to activate a new row (tRCD), another bank can be streaming columns out of its already-open row at full bus speed.

Here's why this matters. A single bank, accessed serially, gives you maybe 10–15 ns per random access. The DDR5-6400 bus, meanwhile, can transfer 64 bits every 0.3125 ns. If you can only feed one bank at a time, you'll utilize maybe 5% of the bus. But pipeline four banks — activate bank 1, then while it's opening, activate bank 2, then 3, then 4 — and by the time bank 1's data is streaming, bank 2 is ready, bank 3 follows, bank 4 next. You can keep the data bus saturated.

The constraint: tFAW. You can't activate banks infinitely fast. The Four Activate Window (tFAW) caps you at four ACTIVATE commands in any sliding window of ~30 ns. This exists because each activate momentarily draws huge current from on-die charge pumps. Exceed tFAW and the chip browns out. DDR5 added bank groups partly to relax this — accesses across groups have lower minimum spacing (tCCD_S) than within a group (tCCD_L).

Concrete example: linked-list traversal vs. array stride. Walking a 64-byte-stride array through 1 GB of DRAM, the memory controller sees sequential addresses, distributes them across banks via address interleaving (typically XOR-based on bits 6–9), and easily hits 8+ outstanding bank operations. You'll measure ~40 GB/s on a DDR5-6400 single channel. Now walk a pointer-chasing linked list: each load depends on the previous, so only one bank is busy at a time. Same hardware, same bus, ~250 MB/s. That's a 160× gap from bank-level parallelism alone.

Rule of thumb: to saturate a DDR5 channel, you need roughly bandwidth × latency = concurrency. At 50 GB/s and 80 ns end-to-end latency, that's ~4 KB in flight, or ~64 outstanding cache-line requests. The MSHRs, LFBs, and reorder buffer all have to be deep enough to keep that many requests alive — and the access pattern has to spread across enough banks for the DRAM to actually serve them in parallel.