2026-05-20
Two wires running parallel on a chip or PCB form a tiny capacitor through the dielectric between them. When the aggressor switches, it shoves charge through that mutual capacitance onto the victim — even though no current source is intentionally driving it. The victim glitches, slows down, or speeds up depending on what its driver is doing at that instant.
Two coupling mechanisms matter:
The damage shows up three ways:
Concrete example: DDR4 data buses run 8-16 bits in parallel at 3200 MT/s. Adjacent bits are aggressors to each other. When 15 bits switch low-to-high simultaneously and one bit goes the opposite way, that lone victim sees its edge slowed dramatically — this is the classic simultaneous switching noise (SSN) worst case. Memory controllers spec a "data bus inversion" (DBI) bit that inverts the byte if more than 4 bits would switch, capping aggressor count.
Rule of thumb: Coupling noise on a victim ≈ Vdd × Cc / (Cc + Cv), where Cv is the victim's total capacitance to ground. If Cc is 20% of Cv, expect ~17% of Vdd as a glitch. At 1.0V supply, that's 170 mV — more than enough to trip a gate with a 500 mV threshold if multiple aggressors gang up.
Defenses, in order of cost:
