A DRAM bit is a capacitor holding ~25 femtocoulombs of charge on a node about 20 attofarads in size. That charge wants to leak away — through subthreshold conduction in the access transistor, through junction leakage at the storage node, and through gate-induced drain leakage (GIDL). Left alone, a "1" decays into a "0" in milliseconds. Refresh is the periodic ritual of reading every row and writing it back before the charge decays past the sense amplifier's detection threshold.

The JEDEC standard for DDR4 mandates a retention time (tREF) of 64 ms at temperatures up to 85°C. Above 85°C, leakage roughly doubles every 10°C, so the spec halves to 32 ms in the "extended temperature range." A typical DDR4 chip has 32,768 rows per bank — divide 64 ms by 32,768 and you get one refresh command every ~1.95 µs. Each refresh takes ~350 ns (tRFC), so refresh steals roughly 18% of memory bandwidth from your workload.

The memory controller issues a REF command, and the DRAM internally cycles through rows using an on-chip refresh counter. You don't address rows individually — the chip tracks where it is. During refresh, the bank is unavailable for reads or writes, which is why high-performance controllers use per-bank refresh (REFpb in LPDDR4/5) to keep other banks accessible.

Real-world example: Servers running at sustained 95°C in hot aisles must use temperature-compensated refresh. The DRAM reports its temperature via the Mode Register, and the controller doubles the refresh rate when the chip crosses 85°C. Skip this and you get silent bit flips — exactly the failure mode that drove Google's 2009 DRAM error study showing 8% of DIMMs experience errors annually, with temperature being the dominant correlate.

The clever trick — Refresh Pausing: Modern controllers track which rows were recently accessed (an ACTIVATE implicitly refreshes a row by reading it into the sense amps and writing it back). These rows don't need an explicit refresh for another 64 ms. Mobile DRAM takes this further with partial array self-refresh (PASR) — your phone refreshes only the regions holding active app data when the screen is off, cutting standby power by 60%+.

Rule of thumb: Refresh overhead = (rows × tRFC) / tREF. As DRAM density doubles, rows double too, but tREF stays at 64 ms — so refresh tax grows linearly with capacity. By DDR5 with 65,536 rows per bank, refresh would consume 35% of bandwidth without the same-bank refresh and fine-granularity refresh tricks JEDEC added specifically to fight this.