Every time a wire on a bus transitions from 0 to 1 or 1 to 0, hardware pays energy proportional to ½CV². On a wide off-chip bus with 5pF per line at 1.2V running at 1GHz, a single transition costs about 3.6pJ. Multiply by 64 wires switching randomly (32 average transitions per cycle) and you're burning ~115mW just moving data — before any actual computation happens. Bus encoding is the art of rewriting the bits on the wire so that fewer of them toggle, without changing the value the receiver sees.

The classic technique is bus invert coding (Stan-Burleson, 1995). Add one extra "invert" wire. On each cycle, compare the new word to the previously-transmitted word. If more than half the bits would flip, invert the entire word and drive the invert line high. The receiver XORs the invert bit back in. For uniformly random data on an 8-bit bus, this cuts the average number of transitions from 4.0 to about 3.27 — an 18% activity reduction for the cost of one wire and one Hamming-distance comparator.

Other flavors target specific traffic patterns:

• Gray coding for address buses that increment sequentially — adjacent addresses differ by exactly one bit, so a linear instruction fetch toggles one wire per cycle instead of ~log₂(N)/2.
• T0 coding adds an "increment" flag: if the new address is prev+stride, freeze the address wires entirely and pulse one control line. Real programs get 60-80% reductions on the address bus.
• Working-zone encoding exploits temporal locality — most accesses hit one of a few active regions, so transmit a small region ID plus an offset instead of a full address.

Real-world example: Intel's Pentium 4 front-side bus used a form of bus-invert on its 64-bit data path. Rambus RDRAM used DBI (Data Bus Inversion) for exactly this reason, and DDR4/DDR5 made DBI mandatory on the DQ lines — the DBI pin flips when more than four of the eight data bits would drive low, cutting SSN (simultaneous switching noise) as much as it cuts energy.

Rule of thumb: Bus-invert saves power only when the encoder/decoder logic burns less than the transitions it eliminates. On short on-chip buses (<2mm), the wire capacitance is so low that the XOR tree and majority voter cost more than they save. Bus encoding pays off when the bus capacitance exceeds roughly 100fF per wire — meaning long global routes, chip-to-chip links, and DRAM interfaces. For short local buses, don't bother.