Flip-flops are the default storage element in synchronous design, but they're not the fastest option. When you need to squeeze the last picosecond out of a design, you rip out the flops and replace them with pairs of level-sensitive latches driven by two non-overlapping clocks (phi1 and phi2). This is how the original MIPS R2000, the DEC Alpha 21064, and most modern high-performance x86 datapaths were actually clocked.

The core idea: A flip-flop is really just two latches glued together with an inverter between their clock inputs. That means every stage of your pipeline pays for two latch delays plus the clock-to-Q of the master. If you split them apart — latch A on phi1, combinational logic, latch B on phi2, more combinational logic, back to latch A on phi1 — you get two "half-cycles" of logic per full clock period, and time can flow freely across the latch boundary.

Non-overlapping is critical. If phi1 and phi2 are ever high simultaneously, data races straight through both latches in one shot, corrupting the next stage. You generate non-overlap with cross-coupled NAND gates and a delay chain — typically 100-300 ps of dead time between phi1 falling and phi2 rising at 1 GHz.

Why it's faster:

• Time borrowing works automatically. If phase 1's logic runs long, the data arrives late at latch B — but latch B is still transparent, so it passes through into phase 2's logic. You've "borrowed" time from the next half-cycle without any explicit skew engineering.
• Latch delay is roughly half a flip-flop's. A transmission-gate latch is 3-4 gate delays; a full master-slave flop is 6-8.
• Setup/hold discipline relaxes. Data only needs to arrive before the latch closes, not before the clock edge.

Rule of thumb: A latch-based two-phase design can hit roughly 15-25% higher frequency than the same logic in a flip-flop-based design, at the cost of much harder static timing analysis and CAD tool support that most commercial flows treat as second-class.

Real-world example: The Alpha 21264 used two-phase latch-based clocking with a 600 MHz target in a 0.35 μm process — a frequency nobody was hitting with flip-flops. The design team used a custom timing analyzer because Synopsys PrimeTime couldn't handle time-borrowing across transparent latches cleanly. Modern GPUs and some Intel cores still use latch pairs in the hottest datapath stages while keeping the control logic flop-based.