Every time a CMOS gate switches, it pays a tax: E = ½CV² per transition, dumped into the substrate as heat. Charge a 10 fF node to 1 V and you've burned 5 fJ — gone forever the moment the PMOS pulls it high through a constant supply. Adiabatic logic refuses to pay that tax. Instead of switching against a fixed rail, it charges the load through a slowly ramping power-clock, then recovers the stored charge back into the source on the way down.

The physics: dissipation in a resistive charging path scales as (RC/T) · CV², where T is the ramp time. Make T much greater than RC and the energy dissipated per cycle approaches zero — asymptotically. The price is speed. You're trading frequency for energy, and the recovery is incomplete in practice (10–50% of CV² is typical), but that's still 2–10× better than static CMOS at the same activity factor.

How it actually works: replace VDD with a trapezoidal or sinusoidal power-clock φ. A standard CMOS gate is rewired so its pull-up network connects to φ instead of VDD. As φ ramps up, the output follows through the pull-up. As φ ramps back down, the charge on the output capacitance flows backward through the same network into φ — which is now a falling rail acting as a charge sink. The power-clock generator (typically a resonant LC tank with a small inductor) catches that returning charge and reuses it on the next cycle. The inductor is the trick: it converts the charge sloshing back and forth into a near-lossless oscillation, with only the inductor's series resistance and switch losses to make up.

Real-world example: 2QN2P and Positive-Feedback Adiabatic Logic (PFAL) families have shipped in passive RFID tags and implantable medical devices, where the entire chip runs on microwatts harvested from an RF field. A PFAL-based 13.56 MHz NFC tag can run its logic at 100 kHz on 1–2 µW — roughly 5× lower than a static CMOS equivalent. The slow ramp isn't a problem because the harvested RF carrier is the power-clock — you get the sinusoid for free.

Rule of thumb: energy savings ≈ 2RC/T compared to static CMOS. If your gate's RC is 100 ps and you ramp φ over 10 ns, you dissipate roughly 1/50th of CV² per transition — assuming an ideal resonant driver. Below T ≈ 5·RC, recovery collapses and you're back to dumping heat.

The catch: routing four-phase overlapping power-clocks across a chip is brutal, leakage doesn't recover at all (it just leaks), and the resonant tank adds area. Adiabatic logic lives in the ultra-low-power niche, not the mainstream.