Every modern x86 core has a dedicated timer integrated into its Local APIC. Unlike the legacy PIT (Programmable Interval Timer) or HPET, which are shared system-wide resources, the LAPIC timer is per-core. This is the hardware that makes preemptive multitasking scale: each core can independently decide "my current thread's time slice expired" without contending for a global timer.

The LAPIC timer is a 32-bit countdown counter. You write an initial value to the Initial Count Register (MMIO offset 0x380), and it counts down toward zero at a frequency derived from the CPU's bus clock divided by a value in the Divide Configuration Register. When it hits zero, it fires a local interrupt — visible only to that core, never traveling across the interconnect.

It has three modes:

• One-shot: Fires once, then stops. Useful for "wake me up in exactly 3.7ms."
• Periodic: Auto-reloads the initial count. Classic tick-driven kernels used this for HZ=1000.
• TSC-Deadline: You write an absolute TSC value; interrupt fires when TSC crosses it. This is what modern Linux uses — it sidesteps the divider entirely and gives nanosecond-precision wake-ups.

Real-world example: When Linux runs in NO_HZ_FULL ("tickless") mode on a CPU-isolated core for low-latency trading or DPDK packet processing, the kernel reprograms that core's LAPIC timer to fire only when the next scheduled event is due — sometimes hours away. The "1000 ticks per second" model is gone; the core executes user code with zero timer interruptions. Switch to TSC-Deadline mode (cat /proc/cpuinfo | grep tsc_deadline_timer) to see if your CPU supports it.

Rule of thumb: LAPIC timer overhead per interrupt is roughly 200-500 cycles on modern hardware. At HZ=1000 on a 3 GHz core, that's ~0.015% pure overhead — negligible for desktops, catastrophic for a core trying to sustain 100ns packet latency. That's why HFT shops disable the tick on isolated cores.

One historical gotcha: the LAPIC timer's countdown frequency depends on the bus clock, which changes when the CPU enters deep C-states. Before TSC-Deadline mode (pre-2010), kernels needed the "always-running APIC timer" (ARAT) feature flag or had to fall back to HPET when cores went idle. Check dmesg | grep -i "lapic.*deadline" to confirm your kernel chose the modern path.