A modern 16 Gb DRAM die has roughly 17 billion cells. At any real manufacturing node, the probability that all of them work is essentially zero — a single dust particle during lithography can kill hundreds. If chipmakers threw away every die with a defective cell, yield would round to zero and DRAM would cost thousands of dollars per gigabyte. Instead, they build every die with spare rows and columns, test the array, and rewire the address decoders to route around the broken parts. The chip you buy is almost never the chip that came off the wafer.

The mechanism is redundancy repair. Each memory bank includes maybe 8 extra rows and 8 extra columns beyond its nominal size — call it a 1024-row bank that physically has 1032 rows. During wafer probe, an automated tester writes patterns to every cell and records which addresses fail. Software then computes a repair solution: which failing rows/columns can be replaced by spares. This is a small combinatorial optimization problem — a single spare row can fix an entire row of bad cells cheaply, while scattered single-bit failures might each need a column spare.

Once the repair solution is known, the tester either fires a laser to physically vaporize polysilicon fuses on the die, or (in modern parts) blows electrical antifuses by punching through a thin oxide with a high voltage. Each fuse state feeds a comparator in the row decoder. When an incoming address matches a "repaired" address stored in fuses, the decoder silently substitutes the spare row instead. Software and even the memory controller never see it.

Concrete example: Micron and Samsung routinely report that 50–70% of dies coming off the wafer have at least one defect, but post-repair yield exceeds 90%. On a 300 mm wafer with ~1000 candidate dies at $30 raw silicon cost per die, that's the difference between $60/die and $300/die shipped cost — redundancy is the reason DRAM is a commodity rather than a luxury.

Rule of thumb: Add spare rows/columns until the marginal die-area cost equals the marginal yield gain. Typically this lands around 2–3% area overhead for 10–30× yield improvement. Beyond ~5% redundancy you're spending silicon to fix problems that a process improvement would solve more cheaply.

Post-package repair (PPR) in DDR4/DDR5 extends this: the BIOS can burn additional antifuses in the field when the memory controller reports a persistent error, letting a server heal itself without a DIMM swap.