Tomasulo tells you what reservation stations do, but the real question is: how does an instruction sitting in one know, within a single cycle, that its operand just became available? That's the job of wake-up and select logic, and it's one of the tightest, most power-hungry loops in a modern CPU.

Every entry in the issue queue holds two source tags — the physical register numbers it's waiting on. When any function unit completes, it broadcasts its destination tag on a set of tag CAM lines that run past every issue queue entry. Each entry XORs the broadcast tag against its stored source tags with a CAM cell. A match asserts a "ready" bit for that operand. When both operand bits are ready, the entry raises a request line.

Then select logic picks winners: multiple entries may become ready in the same cycle, but the machine can only issue N of them (issue width). A priority tree — usually oldest-first, sometimes a matrix arbiter — picks up to N requesters and generates grant signals. Grants gate the operands out of the physical register file (or the bypass network) and drive them to the function units.

Here's the killer constraint: wake-up + select + operand-read must all fit in one cycle if you want back-to-back dependent instructions. Consider a chain ADD r1, r2, r3 → ADD r4, r1, r5. If the first ADD finishes in cycle T, the second must issue in cycle T+1. So the T→T+1 boundary contains: broadcast r1's tag → CAM match → operand-ready OR → request → priority select → grant → operand mux. That whole loop is the "scheduler critical path" and it's often what caps your frequency.

Rule of thumb: the wake-up CAM has O(W × N) cells, where W = issue width and N = queue size. Doubling issue width roughly doubles wake-up power and often lengthens the critical path by ~15%. That's why Intel's Skylake stuck at 4-wide issue for years — the scheduler loop wouldn't shrink at higher frequency without exploding power.

Concrete example: AMD's Zen 4 has a 96-entry integer scheduler, 4 ALU ports, 3 AGU ports. That's 7 destination tags broadcasting per cycle across ~192 source-tag CAM cells (96 × 2). Each broadcast burns picojoules; Zen 4 spends roughly 8% of core power just on scheduler wake-up. Some designs (POWER, older Alpha) split the queue into per-port sub-queues to shrink the CAM at the cost of load-balancing headaches.

When you hear an architect say "we couldn't afford another issue port," this is what they mean: not silicon area, but that one-cycle CAM loop that everything else waits on.