You want 24-bit resolution from a converter built on a 1-bit comparator. That sounds like a contradiction — but sigma-delta (ΣΔ) ADCs do exactly this by sampling absurdly fast and letting digital filters do the heavy lifting. Almost every audio codec, weigh scale, thermocouple front-end, and precision voltmeter uses one.

The core trick: oversampling spreads quantization noise. A traditional Nyquist ADC samples at just above 2× signal bandwidth. Quantization noise (the rounding error of finite resolution) lands evenly across the band from 0 to Fs/2. If you sample 256× faster, that same noise power spreads over 256× more bandwidth. The noise in your signal band drops, even though total noise hasn't changed. Pure oversampling buys you 0.5 bits per 2× — slow progress.

Noise shaping is where the magic happens. A 1st-order ΣΔ modulator wraps the comparator in a feedback loop with an integrator. The integrator's transfer function pushes quantization noise toward high frequencies, away from your signal band. Now oversampling 2× buys 1.5 bits (1st-order) or 2.5 bits (2nd-order). Real audio converters use 4th- or 5th-order loops where each doubling buys 4.5+ bits.

Block diagram of a 1st-order modulator:

• Subtractor: input − feedback (1-bit DAC output)
• Integrator: accumulates the error
• 1-bit comparator: outputs 1 if integrator > 0, else 0 — clocked at the oversample rate
• Feedback DAC: 1-bit, drives ±Vref back to the subtractor
• Decimation filter (digital): low-pass + downsample to recover the multi-bit output at the final sample rate

The output bitstream is mostly 1s when input is near +Vref, mostly 0s near −Vref, and roughly 50/50 at midscale. The density of 1s encodes the analog value.

Concrete example: An audio codec with 48 kHz output and a 256× oversample ratio runs the modulator at 12.288 MHz. A 4th-order loop yields ~120 dB SNR in the 20 kHz audio band — about 20 effective bits. The decimation filter (typically a CIC followed by FIR stages) does most of the chip's gate count.

Rule of thumb: For an Nth-order modulator, doubling the oversample ratio buys roughly (N + 0.5) bits of resolution. So a 3rd-order loop at OSR=64 gains ~21 bits over the 1-bit raw quantizer.

Tradeoff: ΣΔ ADCs are slow (kHz-to-MHz signal bandwidth, not GHz) and have long latency from the decimation filter. They dominate where precision matters more than speed: audio, instrumentation, sensor interfaces.