Every digital system needs clocks, and rarely just one. Your CPU might need 3.2 GHz internally but talks to memory at 1.6 GHz and to a PCIe bus at 100 MHz. A single crystal oscillator can't provide all of these. That's where the Phase-Locked Loop (PLL) comes in — it takes one reference clock and synthesizes others from it.

A PLL has four core components wired in a feedback loop:

• Phase/Frequency Detector (PFD): Compares the reference clock to the feedback clock. Outputs "speed up" or "slow down" pulses proportional to the phase difference.
• Charge Pump + Loop Filter: Converts those pulses into a smooth analog control voltage. The loop filter (typically a low-pass RC network) determines stability and lock time. Too aggressive, and the PLL oscillates. Too conservative, and it takes forever to lock.
• Voltage-Controlled Oscillator (VCO): Outputs a frequency proportional to the control voltage. This is the actual clock generator. In digital implementations (DCOs), this is often a chain of inverters whose delay is tuned by capacitor banks.
• Frequency Divider (÷N): Divides the VCO output before feeding it back to the PFD. This is the multiplication factor. If your reference is 25 MHz and you divide by 40, the VCO locks at 1 GHz.

The math is simple: f_out = f_ref × (N / M), where M is an optional pre-divider on the reference. Want 148.5 MHz (HDMI pixel clock) from a 25 MHz crystal? Set M=2, N=59: 25 × 59/5 = no, better: M=5, N=297/5... In practice, you consult the PLL's datasheet and its valid N/M ranges. FPGA tools calculate this for you.

Real-world example: On a Xilinx FPGA, you instantiate a Mixed-Mode Clock Manager (MMCM) — which is a PLL with fine phase shift capability. Feed it a 100 MHz board oscillator, and configure it to produce 200 MHz for your DDR3 controller, 74.25 MHz for HDMI 720p, and 10 MHz for a SPI peripheral. One primitive, three output clocks, all phase-aligned to the reference.

Jitter is the critical spec. PLLs don't produce perfect clocks — the output edges wander slightly. For a 1 Gbps SERDES link, you typically need under 50 ps RMS jitter. The loop filter bandwidth controls the tradeoff: narrow bandwidth rejects more reference jitter but tracks frequency changes slowly.

Lock time matters at power-on. A typical FPGA PLL locks within 1–10 ms. Your reset logic must hold the entire design in reset until the PLL asserts its locked signal. Releasing reset before lock is a classic bug — the design runs on a garbage clock for a few milliseconds and enters an unpredictable state.

Rule of thumb: PLL loop bandwidth should be roughly 1/10th of the reference frequency. A 10 MHz reference suggests ~1 MHz loop bandwidth for stable operation.