You think of a "CPU" as cores, but on a modern chip the cores are a minority of the silicon. The uncore (Intel's term; AMD calls it the Infinity Fabric / IOD) is everything on the die that isn't a core: the L3 slices, the ring or mesh interconnect, memory controllers, PCIe root complex, the snoop filter / coherence directory, the power control unit (PCU), and the inter-socket links (UPI/xGMI). It runs on its own clock domain and its own voltage rail.

Why split it out? Because cores and I/O have opposite scaling needs. Cores want high frequency and low latency on a small, hot area. Memory controllers and PCIe want wide parallelism, predictable latency, and to stay near the chip edge where the pins live. Putting them on the same clock would either underclock the cores or melt the I/O.

Concrete example — Intel Sapphire Rapids: the chip is four tiles stitched together by EMIB. Each tile has cores plus a slice of the mesh, but the memory controllers and PCIe controllers form a logical uncore that runs at an independent uncore frequency (typically 2.4–3.2 GHz) while cores boost past 4 GHz. AMD Genoa goes further: the I/O Die (IOD) is a separate physical chiplet on an older 6nm process, while the cores live on 5nm CCDs. The uncore literally isn't the same silicon.

Why you should care as a programmer: uncore frequency is a hidden performance knob. When a core misses L2, the request leaves the core's clock domain, crosses an asynchronous boundary into the uncore, traverses the mesh to the right L3 slice, possibly bounces to a memory controller, and comes back. Every clock-domain crossing costs ~1–3 ns of synchronization. If the uncore is in a low power state because the system looks "idle," your latency-sensitive request just got 30 ns slower for no reason your profiler will explain.

Rule of thumb: a remote L3 hit on a server chip is roughly core_cycles_to_L3 + (mesh_hops × 1 cycle uncore) + 2 sync crossings. On a 28-core Xeon mesh, a worst-case hop count of ~10 at 2.4 GHz uncore adds ~4 ns just for transit — explaining why "L3 hit" latency varies from 12 ns to 25 ns depending on which slice owns the line.

This is also why intel_pstate exposes min_perf_pct for cores but Linux has a separate uncore_freq sysfs knob. Pinning uncore to max on a database server can cut tail latency more than pinning core frequency does.