When a modern chip has 64+ cores, you can't wire every core to every other core — you need a network-on-chip (NoC), usually a 2D mesh of routers. The question is: how do you move a 512-bit cache line from router A to router F efficiently?

Store-and-forward is the naive answer: buffer the whole packet at each hop, then forward. If a packet is 8 flits and you have 5 hops, that's 40 cycles minimum, plus you need buffer space for a full packet at every router. Expensive in area and latency.

Wormhole routing is the fix. Break the packet into small flits (flow control units, typically 128 bits wide). The head flit carries the destination and reserves the output port; body flits stream through the reserved path like train cars; the tail flit releases the reservation. Each router only needs a small buffer (a few flits deep), and the packet stretches across multiple routers simultaneously — literally like a worm crawling through the network.

The problem: if the head flit gets blocked (destination port busy), the whole worm stalls. Worse, other packets waiting behind it in the input buffer are blocked too — even if they wanted to go a different direction. This is head-of-line blocking, the same disease that plagues single-queue network switches.

The fix: virtual channels (VCs). Give each physical link multiple logical queues, each with its own flit buffer. A blocked packet on VC 0 doesn't stop packets on VC 1 — they interleave flit-by-flit over the shared wire, arbitrated per cycle. With 4 VCs per link, a stuck packet only wastes 25% of the bandwidth on that hop instead of 100%.

Real example: Intel's Xeon mesh (Skylake-SP onward) uses a 2D mesh with wormhole routing and multiple VCs to separate request, response, and snoop traffic — preventing a stalled response from blocking snoops (which would deadlock the coherence protocol). Tilera's 100-core TILE-Gx did essentially the same trick years earlier at academic scale.

Rule of thumb for latency: wormhole routing latency ≈ H + L/W cycles, where H = hop count, L = packet length in bits, W = flit width. For a 5-hop, 512-bit packet over 128-bit flits: 5 + 4 = 9 cycles. Compare to store-and-forward: 5 × 4 = 20 cycles. That's why every serious many-core chip uses wormhole.

Deadlock warning: VCs must be used with turn restrictions (like dimension-order routing: X first, then Y) or an escape VC — otherwise cyclic buffer dependencies deadlock the whole mesh cold.