This is a final project demonstration from Cornell's ECE 5760 "Advanced Digital Design with FPGAs" course, and it tackles one of the genuinely hard problems in chip design itself: placement. When you synthesize a design onto an FPGA or ASIC, the tool has to decide where to physically locate each logic cell so that wire lengths are minimized and timing closes. Analytical placement reformulates this as a continuous optimization problem — typically solving a quadratic system to find ideal cell locations, then iteratively legalizing them onto the discrete grid.

What makes this project especially interesting is the meta-aspect: the students are using an FPGA to accelerate the algorithm that places logic onto FPGAs. Hunter Adams' ECE 5760 projects are consistently high-quality — students are required to publish detailed project webpages walking through their math, HDL architecture, and results, so the video is best treated as a trailhead leading to a deep technical writeup. If you've ever wondered what Vivado or Quartus is actually doing during the place-and-route step that takes 20 minutes of your life, this is a window into the underlying algorithms.

Adams' channel is a reliable source of substantive FPGA content aimed at engineers, not beginners, and the course material itself is freely available online.