A single-threaded pipeline spends most of its life waiting. A load misses in L1 and stalls for 12 cycles. A branch mispredicts and flushes 15 stages. The ALU sits idle while the front-end refetches. Barrel processors — also called fine-grained multithreaded or interleaved multithreaded processors — solve this by rotating through N hardware threads, issuing one instruction from a different thread every single cycle.

The trick: if you have N threads and a pipeline depth of N stages, no two instructions in flight belong to the same thread. That means zero data hazards, zero control hazards, and no forwarding network needed. The barrel rotates like a revolver's cylinder — thread 0 issues at cycle 0, thread 1 at cycle 1, and by the time thread 0 comes back around, its previous instruction has fully retired. Register file reads never conflict with writes because they happen in different threads.

The cost: single-thread performance is 1/N of a normal pipeline. A 4-thread barrel with a 4-stage pipe gives each thread one instruction every 4 cycles. But if your workload is I/O-bound or memory-bound, the barrel keeps the datapath 100% utilized while a conventional core would be stalled.

Real-world example: The XMOS xCORE family uses 8-way barrel threading. Each thread gets a guaranteed slot every 8 cycles, giving deterministic sub-microsecond response times — that's why xCORE chips are used for software-defined I/O (USB, Ethernet PHY bit-banging) where a normal MCU with interrupts would jitter. Sun's UltraSPARC T1 "Niagara" used 4-way fine-grained threading per core across 8 cores, targeting web-server workloads that spent 75% of their time waiting on memory. Modern GPU warp schedulers are barrel processors at heart — NVIDIA SMs round-robin between ready warps every cycle to hide the 400+ cycle latency of global memory.

Rule of thumb: A barrel with N threads perfectly hides latency up to N cycles. Beyond that, threads start stalling on each other. So if your worst-case load latency is L cycles, you need N ≥ L threads to keep the pipeline full — which is why GPUs run 32+ warps per SM to hide DRAM latency of hundreds of cycles.

Contrast with simultaneous multithreading (SMT / hyperthreading): SMT issues from multiple threads in the same cycle to fill unused issue slots in a superscalar core. Barrel threading issues from one thread per cycle but rotates. SMT preserves single-thread speed; barrels sacrifice it for determinism and simplicity.