You've built a pipeline with valid/ready handshakes (AXI-Stream style). Producer asserts valid, consumer asserts ready, transfer happens on cycles where both are high. Simple, right? Then you route it through five pipeline stages and timing collapses. The culprit is almost always ready.

In a naive design, ready flows combinationally backward through every stage. Stage 5's ready feeds stage 4's ready feeds stage 3's ready... all in one clock cycle. Meanwhile valid and data flow forward through registers. So the return path becomes one giant combinational chain — an AND-tree of "everyone downstream is ready" — and your critical path is 20 gates of stall logic instead of your actual datapath.

A skid buffer breaks this. It's a tiny 2-entry FIFO inserted between stages that registers the ready signal going upstream. But here's the subtle part: if you just register ready, you get a one-cycle window where the upstream still thinks you're ready and sends one more word. That word has nowhere to go — hence the name "skid": the buffer catches the word that skidded in after you said stop.

Why two entries, not one:

• Slot A: the primary data register (the one you're presenting downstream)
• Slot B: the "skid slot" that catches the word already in flight when you deasserted ready

When both slots fill, ready-upstream deasserts. When downstream finally accepts a word, slot B drains into slot A, freeing slot B, and ready-upstream reasserts.

Real-world example: Every AXI-Stream register slice in ARM's AMBA library is a skid buffer. Xilinx calls them "AXI Register Slices" and offers three flavors: forward (register valid/data only), reverse (register ready only), and full (both — this is a true skid buffer). RISC-V vector engines use them at cache-boundary crossings. NoC routers use one per input port so backpressure from one output doesn't stall the entire mesh in one cycle.

The cost/benefit rule of thumb: A skid buffer adds 1 cycle of latency and roughly 2×data_width flip-flops plus ~10 gates of control logic. In exchange, you break a combinational path that might have been 15+ gates of AND-tree spanning thousands of microns of wire. On a 1 GHz design (1 ns period), that's often the difference between meeting timing and missing by 300 ps.

Common mistake: Using a 1-entry "half-buffer" and thinking it's a skid buffer. It's not — it can register ready OR valid/data, but not both. You'll either lose throughput (bubble every other cycle) or fail to break the timing path. If you need both directions registered, you need two entries. There is no cheaper solution — this is a proven lower bound.