Every lock-free data structure you've written — every std::atomic::compare_exchange, every Java AtomicReference.compareAndSet — bottoms out at a single instruction: CMPXCHG on x86, CAS on SPARC. Software treats it as a magic primitive. Hardware has to actually make it atomic across a coherent multi-core system, and the mechanism is surprisingly concrete.

The naive implementation locks the memory bus for the duration: assert LOCK#, do a read-modify-write, release. This is what the original Pentium's LOCK CMPXCHG literally did — every other core stalled. It works, but it doesn't scale past a handful of cores because the bus becomes the bottleneck.

Modern implementations do it entirely in the cache coherence protocol. The sequence on an Intel Skylake core:

• Core issues LOCK CMPXCHG [addr], rbx with expected value in rax.
• L1 cache controller sends a Read-For-Ownership (RFO) on the ring bus, forcing the line into M state (Modified, exclusive) in this core's L1. All other cores invalidate their copies.
• The load-store unit locks the cache line — not the bus. A special bit in the L1 tag array marks the line as "reservation held." Any incoming snoop request from another core gets NACKed until the CAS completes.
• The ALU compares the loaded value against rax. If equal, the store portion writes rbx and updates the cache line. If not, no store occurs but the line still stays in M.
• ZF flag is set based on the comparison. The line unlocks. Snoops resume.

The whole operation is atomic because between the RFO and the unlock, no other core can even observe the line, let alone modify it. The coherence protocol enforces the atomicity — no explicit bus lock needed.

Concrete real-world example: a lock-free stack push using CAS on Skylake. Uncontended CAS takes ~5-6 cycles (L1 hit, line already in M state). Contended CAS with the line in another core's L1 takes ~40-60 cycles just for the RFO snoop round-trip across the ring bus. This is why uncontended lock-free code is fast and contended lock-free code often loses to a well-designed mutex — the CAS itself isn't the cost, the coherence traffic is.

Rule of thumb: a successful CAS on a line already in M state ≈ 5 cycles. A CAS on a line owned by another core on the same socket ≈ 40 cycles. A CAS on a line owned by another socket ≈ 200+ cycles. Multiply by your CAS-retry loop depth to predict lock-free algorithm performance under contention.