Last time you saw how transistors form logic gates. Gates alone are combinational — outputs depend only on current inputs, with no memory. To build anything useful (a CPU, a counter, a state machine), hardware needs to remember. That's where flip-flops come in, and the D flip-flop is the workhorse of all digital design.

The core idea: A D flip-flop captures whatever value is on its D (data) input at the exact moment the clock signal rises (0→1), and holds that value on its Q output until the next rising clock edge. Between edges, D can change freely — the output ignores it.

How it works internally: Two back-to-back latches form a "master-slave" pair. The master latch is transparent when the clock is low (it follows D), and the slave latch is transparent when the clock is high (it copies the master's captured value to Q). The result: Q only changes at the rising edge, giving you a clean, predictable snapshot.

• D — Data input (what you want to store)
• CLK — Clock input (when to capture)
• Q — Stored output
• Q̅ — Inverted output (always the complement of Q)

Real-world example: Every register in a CPU is a bank of D flip-flops. An x86-64 general-purpose register like RAX is 64 D flip-flops sharing a common clock. When the pipeline stage signals "write-back," the rising clock edge captures the computed result across all 64 bits simultaneously. A modern CPU at 5 GHz does this five billion times per second per register.

Critical timing parameters: This is where software engineers first get bitten by hardware reality.

• Setup time (t_su) — D must be stable before the clock edge. Typical: 50–200 ps in modern processes.
• Hold time (t_h) — D must stay stable after the clock edge. Typical: 20–100 ps.
• Clock-to-Q (t_cq) — Delay from clock edge to Q becoming valid. Typical: 30–150 ps.

Rule of thumb for max clock frequency: The slowest path between any two flip-flops determines your speed limit. If combinational logic between two flip-flops has delay t_logic, then:

f_max = 1 / (t_cq + t_logic + t_su)

Say t_cq = 100 ps, t_logic = 500 ps, t_su = 100 ps. Then f_max = 1 / 700 ps ≈ 1.43 GHz. To go faster, you break t_logic into smaller stages with flip-flops between them — that's pipelining, and it's why deeper pipelines enable higher clock speeds (at the cost of latency).

Why not SR or JK flip-flops? The D flip-flop has a single data input, making synthesis tools' jobs trivial — no ambiguous or forbidden input combinations. In practice, 99% of flip-flops in any ASIC or FPGA are D-type. SR and JK are textbook curiosities.