CMOS is a wonderful thing until you try to run it at 10 GHz. The problem is fundamental: CMOS is rail-to-rail. Every gate swings its output from 0 V to VDD and back, dumping CV²f watts of energy per switch and waiting for a big PMOS to drag a heavy capacitance up to the supply. At multi-GHz speeds, you can't afford either. Current-Mode Logic (CML) is the answer, and it's how nearly every SerDes, high-speed clock buffer, and optical driver in your datacenter actually works.

The core idea is a differential pair with a tail current source. Two NMOS transistors share a fixed current I_SS (typically 1–4 mA), and their sources tie to a current sink. Two resistors R_L pull their drains up to VDD. The differential input steers all of I_SS into one branch or the other — never both, never neither. The output swings between VDD and VDD − I_SS·R_L, typically only 300–400 mV peak-to-peak per side.

That small swing is the whole trick. Less voltage swing means less charge to move (Q = CV), which means faster edges for the same current. The transistors also stay in saturation the entire time — they never enter cutoff or triode — so there's no slow subthreshold turn-on delay. It's like a runner who never comes to a full stop between sprints.

Real-world example: The clock buffers inside an Intel Xeon's on-die serial links, and every 25/50/100G Ethernet PHY, use CML. A CML XOR (used as a phase detector in CDR loops) is just two stacked differential pairs sharing a tail current — three transistor stages tall, and it runs cleanly at 25 GHz on 7nm.

Rule of thumb — CML power: Static power is simply P = I_SS × VDD, and it's constant regardless of frequency. A 2 mA tail on a 1.0 V rail burns 2 mW whether the gate switches at 1 Hz or 10 GHz. Compare that to CMOS: at 10 GHz with 20 fF load and 1 V swing, CMOS burns C·V²·f = 20 fF × 1 V² × 10 GHz = 200 μW dynamic per gate. Sounds like CMOS wins — until you realize CMOS can't reach 10 GHz in the first place at reasonable process nodes without prohibitive buffer chains.

The tradeoffs are real: CML burns power when idle, needs bias circuitry, requires matched differential routing, and consumes headroom (you need VDD > V_swing + V_DS,sat + V_tail, roughly 800 mV minimum). But when you need to move a bit every 40 picoseconds, it's the only game in town.