Every CMOS designer learns that transistors "turn on" at the threshold voltage Vt (typically 0.3–0.5V in modern nodes). Below that, the transistor is "off" — but it's not really off. A small sub-threshold leakage current still flows, growing exponentially with Vgs. For decades this was treated as a parasitic nuisance. Then someone asked: what if we compute with that leakage current instead of fighting it?

That's sub-threshold logic. You drop the supply voltage below Vt — typically 0.2V to 0.4V — and let the "leakage" become your signal current. The transistor is technically in weak inversion, where drain current follows an exponential law:

I_D ≈ I₀ · exp((V_GS − V_t) / (n·V_T))

where V_T is the thermal voltage (~26 mV at room temp) and n is the sub-threshold slope factor (~1.3). This is the same exponential as a bipolar transistor — sub-threshold MOSFETs behave like BJTs.

The energy win is huge. Dynamic energy scales with V_DD². Dropping from 1.0V to 0.3V cuts energy per operation by roughly 11×. For circuits where speed doesn't matter — wristwatches, hearing aids, implanted glucose sensors, RFID tags — sub-threshold operation extends battery life from months to decades.

The catch is severe. Drive current drops by 4–6 orders of magnitude, so clock frequencies fall from GHz to kHz or low MHz. Worse, the exponential I-V relationship makes everything extremely sensitive to variation:

• Temperature: 10°C change can shift delay by 2×
• Process variation: a 50 mV Vt mismatch between two transistors changes their current by ~7×
• Noise margin: with V_DD = 0.3V, you have ~150 mV of margin — supply noise easily corrupts logic

Real example: The MIT "Phoenix" processor (2008) ran at 0.5V with peak energy of 2.6 pJ/cycle — small enough that a 1 mm² solar cell under indoor lighting could power it. It enabled implantable medical sensors that never need battery replacement.

Design rules of thumb:

• Use balanced pull-up/pull-down stacks — single-transistor stacks beat tall NAND/NOR stacks because series-stacked sub-threshold transistors compound variation
• Up-size transistors aggressively (often 10–100× minimum) to average out random dopant fluctuation
• Use high-Vt transistors paradoxically helps — they have steeper sub-threshold slopes
• Add adaptive body biasing to track temperature and process

The minimum-energy operating point isn't actually at zero volts — leakage energy eventually dominates dynamic energy. For most processes, the sweet spot is around 0.3–0.4V, where total energy per operation hits a minimum roughly 10× lower than nominal operation.