The asker is selecting a configuration PROM for an iCE40LP4K-CM121. Lattice's programming and configuration guide states the SPI flash "must be ready to accept commands 10µs after meeting its power-on conditions." Every SPI NOR flash they've checked specifies a power-up-to-ready time (typically called tVSL or tPU) of 100µs at minimum, often 10ms. They're stuck — even Lattice's own breakout boards seem to use parts that don't meet this 10µs spec.

Why this is interesting: It's a great example of a datasheet "requirement" that, on inspection, doesn't reflect how the silicon actually behaves. Anyone building a real iCE40 board hits this and panics. Reconciling the docs with what every reference design actually does requires understanding the FPGA's boot state machine, not just the timing tables.

The resolution: The 10µs figure is the worst-case window in which the iCE40 starts polling — it isn't a hard timeout that bricks the boot. In SPI master mode (SPI_SS_B tied appropriately), the iCE40 issues a 0xAB Release-Power-Down / Read-ID command and then a 0x03 Read at address 0. If the flash NACKs or returns garbage because it's still in its power-up reset, the FPGA simply re-reads. The configuration logic tolerates a flash that wakes up later than 10µs because the read of the bitstream header byte 0x7E won't match until valid data appears. Lattice's own AN can be read this way; their reference designs use Winbond W25Q-series and Macronix MX25 parts with 100µs+ power-up times, and they work.

Practical approach:

• Pick any standard 3.3V SPI NOR flash in the right density — Winbond W25Q32JV, Macronix MX25L1606, ISSI IS25LP032. Match the iCE40LP4K bitstream (~80kbit, so 1Mbit flash is plenty; size up if you want overlay/golden images).
• Hold CRESET_B low through a small RC delay (~1ms) on power rails so the FPGA only starts its config sequence after the flash is comfortably out of tPU. This sidesteps the spec question entirely.
• If you have a tight power-on timing budget, look for parts with a fast tVSL — Adesto/Dialog AT25SF series spec ~50µs, still not 10µs but close.

Gotchas: (1) The flash must support the 0x03 Read opcode at clock speeds the iCE40 generates during boot (~25MHz default; some "high-speed only" parts require 0x0B Fast Read with a dummy byte and won't boot). (2) Power sequencing matters more than wake-up time — if VCCIO_2 rises slowly, the FPGA may begin configuration before the flash has stable I/O. (3) Don't share the config SPI bus with another master unless you tri-state during boot.