If you put a 100 MHz square wave on a PCB trace, the FCC sees a giant spike at 100 MHz on its spectrum analyzer — plus harmonics at 300, 500, 700 MHz, etc. Each spike concentrates real RF energy at one frequency, and the regulatory limit is measured per frequency bin. Cross the limit and your product doesn't ship. Spread Spectrum Clocking is the hardware trick that fixes this without lowering the actual clock rate: instead of running at exactly 100 MHz, you modulate the clock frequency up and down by a small amount (say ±0.5%) at a slow rate (say 33 kHz). The total energy stays the same, but it's now smeared across a band of frequencies, so the peak in any one bin drops by 10–20 dB.

How it's built: SSC lives inside the PLL. The feedback divider isn't fixed — it's modulated by a small triangle or "Hershey-kiss" profile generator. As the divider value sweeps, the PLL's output frequency sweeps with it. Triangle modulation is common because it spreads energy uniformly; the Hershey-kiss profile is shaped to flatten the spectral peak even more. Modulation is almost always down-spread (e.g., nominal frequency to nominal −0.5%) so the average frequency never exceeds the spec — important for SATA, PCIe, and USB where the link must stay within timing budget.

Real-world example: PCIe Gen3 explicitly allows SSC at −0.5% with a 30–33 kHz modulation rate. The reference clock at the root complex and the endpoint must use the same SSC profile, or the CDR at the receiver can't track the wandering frequency. This is why you'll see "SSC ON/OFF" as a BIOS option — if you mix an SSC source with a non-SSC sink across a long cable, the receiver's PLL bandwidth may be too narrow to follow, and the link fails.

Rule of thumb: EMI peak reduction in dB ≈ 10·log₁₀(spread_bandwidth / resolution_bandwidth_of_analyzer). For a 100 MHz clock with ±0.5% spread (1 MHz total) measured with a 120 kHz EMI receiver bandwidth: 10·log₁₀(1000/120) ≈ 9.2 dB reduction. Push the spread to ±1% and you gain another 3 dB — but you also push the SerDes CDR harder. Most designs settle at 0.5% as the sweet spot between EMI relief and link robustness.

The cost SSC imposes on the rest of the system: any logic that compares the SSC clock to a non-SSC reference sees a wandering phase. PLLs downstream need enough loop bandwidth (typically >1 MHz) to track the modulation, and FIFOs between SSC and non-SSC domains must be sized to absorb the worst-case frequency offset over the modulation period.