You already know ARM is RISC and x86 is CISC, but that distinction stopped being meaningful around 1995. Modern x86 chips decode complex instructions into RISC-like micro-ops internally. The real architectural differences that matter today are subtler and more interesting.

Instruction encoding: fixed vs variable width. ARM (AArch64) uses fixed 32-bit instructions. x86-64 instructions range from 1 to 15 bytes. This single decision cascades everywhere. Fixed-width means ARM can trivially calculate "the instruction 4 slots ahead starts at PC+16" — making frontend fetch and branch prediction alignment simple. x86 must discover instruction boundaries before it can decode, requiring a pre-decode stage and instruction boundary markers in the L1I cache. Intel dedicates meaningful transistor budget to this problem alone.

Register architecture. AArch64 has 31 general-purpose 64-bit registers. x86-64 has 16 (expanded to 32 with APX/Intel's recent extensions). More architectural registers means less register pressure, fewer spills to the stack, and less dependence on the rename engine to hide the shortage. A typical AArch64 function prologue touches fewer memory operations than its x86 equivalent.

Memory model. This is where it gets consequential for programmers. x86 enforces Total Store Order (TSO) — stores are seen by all cores in program order. ARM uses a weakly ordered model — stores can be reordered unless you explicitly insert barrier instructions (DMB, DSB). x86's stronger model means fewer surprises in concurrent code but requires the hardware to maintain store ordering with larger store buffers and more snooping. ARM's weak model trades programmer convenience for hardware simplicity and power savings. When porting lock-free data structures from x86 to ARM, missing barriers are a classic source of bugs that appear only under load.

Condition codes vs conditional selection. x86 sets flags as a side effect of most ALU operations, creating implicit data dependencies. AArch64 only sets flags when you ask (the S suffix), and provides conditional select/increment instructions (CSEL, CSINC) that let you write branchless code naturally. Where x86 needs a compare, a conditional jump, and two paths, ARM often uses a compare followed by CSEL — one instruction replacing an entire branch.

Power efficiency rule of thumb: at equivalent performance levels, ARM designs typically consume 30-50% less power. Apple's M-series demonstrated this: the M1 matched a 35W Intel i7 at roughly 10W for single-threaded work. The gap comes not from one big difference but from accumulated savings — simpler decode, fewer memory accesses from more registers, and the weak memory model requiring less ordering hardware.

Real-world example: when Apple transitioned from x86 to ARM, Rosetta 2's translation layer handled the memory model mismatch by always inserting barriers for translated x86 code, preserving TSO semantics at the cost of roughly 20% performance — a direct tax for the architectural difference.