Daily Digital Circuits: Sample-and-Hold Circuits: The Analog Snapshot That Freezes a Signal Long Enough to Digitize It

Sample-and-Hold Circuits: The Analog Snapshot That Freezes a Signal Long Enough to Digitize It

2026-07-16

Every ADC you've read about assumes its input is stationary during conversion. A SAR ADC needs 12 clock cycles of stable input to resolve 12 bits. A pipeline ADC needs the signal held constant while it propagates through five stages. Real signals don't cooperate — they move. The sample-and-hold (S/H) circuit is the workhorse that takes a snapshot of a fast-moving analog signal and freezes it long enough for the converter to think.

The topology is embarrassingly simple: a MOSFET switch and a hold capacitor. When the switch closes ("track" phase), the cap follows the input through the switch's RC. When the switch opens ("hold" phase), the cap retains that voltage while the ADC digitizes it. Two components. Four ways to ruin it.

Charge injection: When the NMOS switch turns off, the channel charge (~C_ox·W·L·(V_GS − V_t)) has nowhere to go and dumps roughly half onto the hold cap. On a 1 pF cap with 10 fC of injected charge, you've just added 10 mV of offset — that's 40 LSBs on a 12-bit, 1 V-range ADC.
Clock feedthrough: The gate-to-drain overlap capacitance capacitively couples the clock edge directly onto the held node. Same failure mode, different mechanism.
Aperture jitter: The exact instant the switch opens has picoseconds of uncertainty. For a full-scale sine wave, jitter noise voltage is roughly V_pp·π·f_in·t_jitter. At 100 MHz input and 1 ps of jitter, you've eaten 314 μV — the noise floor of a 14-bit ADC.
Droop: Subthreshold leakage through the "off" switch and the ADC's input impedance slowly bleeds the cap. Droop rate = I_leak / C_hold.

Rule of thumb for sizing the hold cap: pick C_hold so that droop during one conversion time is less than half an LSB. If you're holding for 1 μs with 1 nA of leakage on a 1 V, 12-bit ADC (LSB = 244 μV), you need C ≥ I·t / (LSB/2) = 1 nA · 1 μs / 122 μV ≈ 8 pF. Bigger is safer but slows tracking.

Real-world example: Analog Devices' AD9445 is a 14-bit, 125 MSPS pipeline ADC. Its front-end S/H uses bottom-plate sampling (opening the ground-side switch a hair before the input-side switch) so signal-dependent charge injection cancels to first order. It also uses differential dummy switches — half-sized transistors driven by the inverted clock that inject equal-and-opposite charge. Without these tricks, the ADC couldn't hit 73 dB SNR.

See it in action: Check out PUES PIÉNSENLO by Homo Deus to see this theory applied.

Key Takeaway: A sample-and-hold is two components and four failure modes — charge injection, clock feedthrough, aperture jitter, and droop — and every one of them sets a hard ceiling on the effective resolution of the ADC downstream.

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