In an out-of-order core, the scheduler wakes up an instruction the cycle its operands become ready. But loads are a problem: you don't know if a load hits L1 until the tag comparison completes, and L1 hit latency (say, 4 cycles) is much shorter than L2 latency (12+ cycles). If the scheduler waits for hit/miss confirmation before waking dependents, every load pays L2-hit latency in wakeup delay. So modern schedulers speculate that loads hit L1 and wake up consumers early — betting on the common case.

The mechanism: when a load issues, the scheduler starts a countdown equal to L1 hit latency. Just before the load's result would be available, it broadcasts wakeup to dependent instructions in the issue queue. Those dependents read their other operands, arrive at execute, and grab the load's result off the bypass network. If the load actually hits L1, everything works — you've saved N cycles per dependency chain.

But if the load misses, the dependents already fired with garbage. Now you need selective replay: squash the speculatively-woken instructions, keep them in the issue queue, and re-wake them when the real data arrives from L2. The Pentium 4 famously used this technique — and its replay logic was so aggressive that a single load miss could trigger a cascade of replays. If the load's dependent was itself a load, and its consumers were speculatively woken, you get a "replay storm" that torpedoes IPC.

The tricky part is tracking the speculation shadow: every instruction woken based on an unresolved load must remember which loads it depends on. When a load misses, hardware walks the dependency graph and squashes anything downstream. Cheap implementations replay too much (every instruction in flight after the load); expensive implementations track exact dependencies.

Rule of thumb: speculative wakeup pays off when L1 hit rate exceeds ~90% and the misprediction penalty (replay cost) is less than the saved latency times the hit rate. For a 4-cycle L1 hit vs 12-cycle L2 hit with 95% hit rate: savings = 0.95 × 8 = 7.6 cycles per load; replay cost must stay under that. If your replay logic re-issues 4 instructions on a miss, you break even at ~7.6/4 ≈ 2 cycles of extra replay latency per instruction — very tight.

Modern designs (Intel Sunny Cove, AMD Zen 3+) use more conservative scheduling with narrower speculation windows and smarter dependency tracking to avoid P4-style replay pathology.