Every load and store needs an address before it can hit the cache. That address is rarely a constant — it's something like [rbp + rcx*8 + 0x40]. Computing it is a real arithmetic operation, and modern CPUs dedicate specialized hardware to it: the Address Generation Unit (AGU). Putting address math on the regular ALUs would block actual computation behind every memory access.

An AGU computes the canonical x86-style addressing mode in one cycle:

effective_address = base + index * scale + displacement

The scale is a fixed shift (1, 2, 4, or 8), not a real multiply — it's just wiring. The displacement is an immediate baked into the instruction. So an AGU is essentially a 3-input adder with a barrel-shifter on one leg. Cheap, fast, and replicated.

Why multiple AGUs matter: A modern Intel Golden Cove core has three AGUs — two for loads, one for store-address generation, plus a dedicated store-data port. Zen 4 is similar. That's why a core can sustain two loads + one store per cycle: the AGUs are the bottleneck, not the cache itself.

Real example — pointer chasing vs. array walking:

• Array walk: sum += a[i] — address is base + i*4. The AGU computes it from already-known registers, so the load issues immediately. The cache miss is the only latency.
• Linked list: p = p->next — the address is the result of the previous load. The AGU can't fire until that load completes. You get the AGU latency plus the cache latency, serially. This is half the reason pointer chasing is so painful.

The complex-addressing-mode penalty: On some microarchitectures, addressing modes with both an index and a non-zero displacement ([rax + rcx*8 + 16]) take an extra cycle of load latency vs. simple [rax]. Intel calls this the "complex AGU" path. Rule of thumb: simple [reg] or [reg+disp] loads are 4 cycles to L1; [reg+reg*scale+disp] can be 5. Tight loops with load-use chains feel this.

Why this design wins: Address math is independent of data math. By giving it its own ports and its own simple adders, the CPU can sustain memory bandwidth while the main ALUs grind on whatever the loaded data feeds. Take the AGUs away and even a 10-wide core would starve.