Modern CPUs need to feed wide back-ends with multiple loads per cycle. Apple's M1 sustains 3 loads/cycle; Intel's Golden Cove does 3 loads + 2 stores. There are two ways to build that bandwidth, and they have very different costs.

Option 1: Multi-ported SRAM. Add physical read/write ports to every cell. A true dual-ported SRAM cell needs roughly 8 transistors instead of 6, plus extra wordlines and bitlines. Going from 1 port to 2 ports roughly doubles the area of the data array. Going to 3 ports is worse than 3x because routing congestion explodes. Beyond 2 ports, nobody actually does this for L1.

Option 2: Banking. Split the cache into N independent banks, each single-ported, addressed by some bits of the line offset (e.g., bits [5:3] of the address pick one of 8 banks within a 64-byte line). Multiple accesses proceed in parallel only if they hit different banks. Cheap in area — but you pay in bank conflicts.

The conflict math. Assume B banks and N independent accesses per cycle with uniformly random bank selection. The probability all N hit distinct banks is:

• P(no conflict) = B! / ((B-N)! · B^N)
• For B=8, N=2: 8·7/64 ≈ 87.5% — one conflict every 8 cycles
• For B=8, N=3: 8·7·6/512 ≈ 65.6% — one conflict every 3 cycles
• For B=16, N=3: ≈ 82%

This is why AMD Zen 2's L1D used 16 banks of 4 bytes each to support 2 loads + 1 store: the bank count had to grow faster than the port count to keep conflict probability manageable.

Real-world example. Intel Sandy Bridge's L1D was 8 banks of 8 bytes. With 2 loads/cycle, you'd hit a bank conflict whenever two loads addressed the same bank (bits [5:3] equal) in different cache lines. A naïve memcpy doing 8-byte loads from two arrays that happened to be aligned modulo 64 would conflict on every cycle. Haswell fixed this by adding a second load port with independent bank selection logic — effectively widening to a quasi-dual-ported design via a hybrid scheme.

Rule of thumb. To sustain N accesses/cycle with under 10% conflict rate, you need roughly B ≥ 2N² banks. That's why 3 load ports demands 16+ banks, and why nobody is building 4-load CPUs without exotic interleaving — the bank array becomes a wiring nightmare before the SRAM cells do.

Port width sells; bank count is what you actually pay for.