Standard CMOS gates use complementary pairs: a PMOS network pulls the output to VDD, an NMOS network pulls it to GND. Every input drives a gate terminal, never a source or drain. Pass transistor logic (PTL) breaks that rule. The input signal itself flows through the transistor channel to the output, with another signal controlling the gate. The transistor acts as a switch, not an amplifier.

The classic example is a 2:1 multiplexer. In CMOS, you'd need an inverter plus AOI gates — roughly 10 transistors. In PTL, you need exactly two NMOS transistors: one passes A when select is high, the other passes B when select is low. Four transistors with the complementary pass-gate (CPL) variant. That's a 2-3x area win.

But there's a brutal catch. An NMOS transistor passes a strong 0 but a weak 1. When you try to pass VDD=1.0V through an NMOS, the output only reaches VDD − Vt ≈ 0.6V because the transistor turns itself off as the source voltage approaches the gate voltage. Your "logic 1" is degraded. PMOS has the opposite problem — strong 1, weak 0.

This is why real designs use transmission gates: an NMOS and PMOS in parallel, controlled by complementary signals. Now both polarities pass cleanly. Cost: you need both the control signal and its inverse, plus 4 transistors instead of 2. Still beats full CMOS for muxes and XOR gates.

XOR is where PTL really shines. Full CMOS XOR needs 12 transistors (or 8 with shared inverters). A pass-transistor XOR with transmission gates does it in 6. Multipliers and adders — which are XOR-heavy — get noticeably smaller. ARM's early low-power cores used pass-transistor adders extensively.

Rule of thumb: threshold drop is roughly Vt ≈ 0.3-0.5V in modern processes. At VDD=1.0V, a single NMOS pass transistor delivers ~0.5-0.7V — barely above the next stage's switching threshold. After 2-3 cascaded pass transistors, you've lost so much signal that you must insert a CMOS buffer to restore levels. This is why PTL chains are kept short and always terminated by a static CMOS gate.

The other gotcha: PTL outputs aren't actively driven when all pass transistors are off. The output node floats, holding its last value on parasitic capacitance — for nanoseconds, before leakage corrupts it. Always ensure at least one pass path is enabled, or add a keeper.