The asker wants a clear, mechanical description of the Line-Fill Buffer (LFB) on post-Haswell Intel cores: what fields each entry holds, whether the LFB stores the cache line payload or merely tracks the outstanding request, and how it interacts with the L1D, L2, and the rest of the memory subsystem (store buffer, super-queue, etc.).

This is hard because Intel's public documentation is deliberately sparse here. Most of what we "know" about the LFB comes from patents, SDM scraps, optimization manual hints, performance-counter behavior (L1D_PEND_MISS.FB_FULL, L1D.REPLACEMENT, OFFCORE_REQUESTS_BUFFER.SQ_FULL), and side-channel research (MDS/RIDL exposed surprising LFB internals). The structure also shifted across generations — Haswell had 10 LFBs per core, later parts added a separate Super Queue (SQ) for L2-miss traffic, and Sunny Cove reshuffled the path again.

A solid answer should distinguish three roles the LFB plays simultaneously:

• Miss Status Holding Register (MSHR): tracks outstanding L1D misses — physical address, request type (RFO / read / prefetch), originating load/store uop IDs, MESI state expected on return.
• Write-Combining Buffer: for WC stores (and NT stores), the entry does hold a full 64-byte payload plus a per-byte valid mask, allowing partial writes to coalesce before eviction.
• Refill data path: when the response from L2/L3/DRAM arrives, the line lands in the LFB entry, dependent loads can be satisfied directly from the LFB (early-restart / critical-word-first), and the line is then written into L1D and the entry is freed.

So the short answer is: yes, the LFB holds the payload, not just the request. That's why MDS attacks (Fallout, RIDL, ZombieLoad) could leak data through it.

Direction for a definitive answer: cite the Intel Optimization Reference Manual section on the L1D ("up to 10 outstanding misses"), the patents around the fill buffer / WC buffers, and Travis Downs / Henry Wong / Agner Fog's measurements. Cross-reference the MDS papers for the post-2018 understanding of LFB partitioning between SMT siblings.

Gotchas:

• The LFB is not the Super Queue — confusing them is the most common error. SQ tracks L2 misses going off-core; LFB tracks L1D misses.
• NT stores allocate LFB entries but bypass L1D on eviction.
• FB_FULL stalls are often the real bottleneck in "memory-bound" code well before DRAM bandwidth saturates — ~10 entries × 64B / latency caps single-thread bandwidth (Little's Law).
• SMT shares LFB entries statically-partitioned in some generations, competitively in others — affects benchmarking.