You'd think a copper wire on a chip just sits there carrying electrons. It doesn't. At the current densities inside a modern IC — often 1–10 MA/cm², millions of times what your house wiring carries — the electrons literally knock metal atoms out of place as they flow past. Over months or years, atoms migrate downstream, leaving voids upstream and hillocks downstream. Eventually a void grows big enough to open the wire, or a hillock shorts to a neighbor. Your chip dies.

This is electromigration (EM), and it's one of the dominant wear-out mechanisms in modern silicon. It's why your "solid-state" chip has a finite lifetime even with no moving parts.

The physics: high-energy electrons transfer momentum to metal atoms via "electron wind force." Aluminum is especially vulnerable; copper is better but not immune. Heat accelerates it exponentially — every 10°C roughly doubles the rate.

Black's equation is the rule of thumb every layout engineer knows:

MTTF = A · J⁻ⁿ · exp(Eₐ / kT)

where J is current density, n is typically 2, Eₐ is activation energy (~0.7 eV for copper), and T is absolute temperature. Translation: halve the current density, get 4× the lifetime. Drop the temperature 10°C, get roughly 2× the lifetime.

Real-world example: NVIDIA's RTX 4090 power delivery scandal in 2022–2023. The 12VHPWR connector melted because contact resistance caused localized heating, which accelerated electromigration in the contact pins, which raised resistance further, which caused more heating. A thermal-electromigration runaway. The fix was a redesigned connector (12V-2x6) with longer sense pins to ensure full seating before current flow.

How chip designers mitigate it:

• Widen power/ground wires — lower current density. Top-level metal is often 10–100× wider than signal wires for this reason.
• Use multiple vias — never connect two metal layers with one via; vias are EM hotspots. Design rules typically require 2–4 redundant vias on power nets.
• Bidirectional AC currents help — signal wires fare better than power because momentum transfer averages out. DC-only nets (Vdd, Vss) are the worst.
• Blech length effect: short wires below ~10 µm can survive higher current densities because mechanical stress back-pressure stops atom flow before voids form.
• Cap the per-wire current in EDA tools. Cadence and Synopsys flag any wire exceeding the foundry's J_max during signoff.

Rule of thumb: for a 100 nm-wide copper wire at 105°C, J_max is roughly 1 mA per µm of width. A wire carrying 5 mA needs to be at least 5 µm wide, or it won't hit the 10-year reliability target.