The classic op-amp integrator inverts. That's fine for a lot of signal processing, but sometimes you need positive-going output for positive-going input — driving a scope timebase, ramping a control voltage, or feeding a downstream stage that expects the correct polarity. Cascading two inverting stages works but doubles the noise, offset, and parts count. The Deboo integrator solves this with a single op-amp by exploiting the Howland current-source topology.

How it works: The circuit uses a non-inverting op-amp with matched resistor networks and a grounded capacitor on the non-inverting input. The op-amp forces a current into the capacitor proportional to V_in, so the cap voltage ramps linearly. Because we're using the non-inverting input, the output tracks in the same direction as the input — no sign inversion.

Standard topology:

• Input resistor R to the non-inverting pin
• Capacitor C from non-inverting pin to ground
• Feedback network: R from output to inverting pin, R from inverting pin to ground
• Second R from V_in to non-inverting pin (matched to feedback R)

With all four resistors equal, the transfer function becomes V_out(s) = V_in(s) / (sRC) — a pure non-inverting integrator with time constant τ = RC.

Real-world example: You're building a triangle-wave generator for a Class-D audio modulator, and the comparator downstream expects a positive ramp on positive input. You want a 20 kHz triangle from a ±5 V square wave. Pick RC to yield a 25 µs half-period ramp of 5 V peak: with a 5 V step input, dV/dt = V_in/(RC) = 5 V / 25 µs = 200 kV/s. Choose C = 1 nF, then R = 5 V / (200,000 × 1 nF) = 25 kΩ. Use four matched 25 kΩ 0.1% resistors — matching is critical.

The catch — resistor matching: The Deboo depends on the Howland balance condition. Any mismatch in the four resistors creates a finite input impedance at DC, which either causes the output to run away to a rail (positive feedback) or bleed off the integration (negative feedback). Rule of thumb: use 0.1% resistors minimum, and if you need long integration times (>10 ms), consider a reset switch (JFET or analog switch) across C to periodically zero the output.

Bonus: Because the capacitor is grounded (not floating like the inverting integrator's feedback cap), you can use polarized electrolytics for very long time constants — as long as the DC bias stays positive.