You know flip-flops store bits and you understand timing constraints. Now let's chain flip-flops together to count — and discover why the naive approach breaks at speed.

The Ripple Counter (Asynchronous)

The simplest counter: take a T flip-flop (toggle on every clock edge), and feed its output as the clock to the next flip-flop. Bit 0 toggles every cycle, bit 1 toggles every time bit 0 falls, bit 2 toggles when bit 1 falls — classic binary counting. It's called "ripple" because the clock ripples through the chain.

Here's the problem. Each flip-flop adds its propagation delay (t_pd) before the next stage can react. For an N-bit ripple counter, the worst-case delay before the output is valid is N × t_pd. With a typical FPGA flip-flop t_pd of 2ns, an 8-bit ripple counter needs 16ns to settle. During that settling window, the outputs show transient glitch states — the counter might briefly read 0b0111 → 0b0110 → 0b0100 → 0b1000 as it transitions from 7 to 8. If any combinational logic samples those intermediate values, you get spurious behavior.

The Synchronous Counter

Every flip-flop shares the same clock. Instead of cascading clocks, you use combinational logic to compute when each bit should toggle. Bit 0 always toggles. Bit 1 toggles when bit 0 is high. Bit 2 toggles when bits 0 AND 1 are both high. The general rule: bit N toggles when all lower bits are 1.

All outputs update simultaneously on the same clock edge. No ripple, no glitch states. The tradeoff: you need an N-input AND gate for the highest bit, which grows with counter width. For a 32-bit counter, that's a 31-input AND — in practice, you use carry lookahead or carry chain structures (the same trick from adder design) to keep the logic depth manageable.

Real-World Example: Timestamp Counters

Every modern CPU has a cycle counter (x86's TSC, ARM's CNTPCT). These are wide synchronous counters (48-64 bits) running at full clock speed. A ripple design at 3GHz (t_pd ≈ 0.1ns) would need 6.4ns to settle for 64 bits — that's nearly 20 clock cycles of invalid output. Synchronous design keeps the counter valid every single cycle.

Rule of Thumb: Your maximum ripple counter frequency is f_max = 1 / (N × t_pd). For an 8-bit counter with 2ns flip-flops, that's 62.5 MHz — fine for a slow LED blinker, unacceptable for anything sampled by other logic.

When Ripple Counters Are Acceptable: Prescalers in low-power clock dividers where you only care about the MSB, or asynchronous event counters read by software (where you implement a read protocol that handles metastability). Everywhere else, use synchronous.