When multiple instructions in the issue queue become ready in the same cycle, the scheduler faces a problem: which one goes first? Picking randomly works, but it's bad for performance. The right answer is almost always oldest-first, because older instructions are more likely to be blocking dependents downstream. The hardware that makes this decision in a single clock cycle is the select logic, and its memory of who-came-first is the age matrix.

The naive approach — tag each instruction with a sequence number and compare — doesn't scale. Comparing 64 entries pairwise with multi-bit counters blows your timing budget. Real CPUs use an age matrix: an N×N bit array where matrix[i][j] = 1 means entry i is older than entry j. When an instruction is allocated to slot i, row i is set to all 1s (older than everyone) and column i is cleared. When it deallocates, both row and column zero out.

To pick the oldest ready instruction, the select logic ANDs each row with the "ready" vector and the "wants-this-port" vector. If the result for row i is all zeros across ready entries, then nobody ready is older than i — so i wins. This collapses to a wide AND and a priority encoder, both of which fit in one cycle even at 5 GHz.

Concrete example: Intel's Skylake has a unified 97-entry scheduler feeding 8 execution ports. Each port needs its own select tree because two instructions can't issue to the same port in the same cycle. That's eight separate oldest-ready picks per cycle, all running in parallel against the same age matrix. The matrix itself is ~9,400 bits (97×97) — tiny compared to the data it gates.

Rule of thumb: Age matrix area scales as O(N²), select logic delay scales as O(log N). At N=64 you're looking at ~4,000 bits and ~6 gate levels — comfortably one cycle. Push N to 256 and the matrix balloons to 65,000 bits, which is why modern schedulers cap entries and instead grow the physical register file (which scales linearly) to hide more latency.

One subtle wrinkle: age isn't always program order. Some designs use "allocation age" (when the instruction entered the scheduler) rather than dispatch order, because branches can squash whole swaths of the matrix and renumbering is expensive. The matrix is built to handle holes gracefully — cleared columns just never win.