A standard floating-point pipeline that computes A×B+C does it in two rounded steps: multiply A×B, round to 53 bits, then add C, round again. Two roundings means two chances to lose precision. A fused multiply-add (FMA) computes the whole expression with a single rounding at the end — and it's typically faster than doing them separately, because the internal datapath is fatter and doesn't collapse the intermediate product back into a 53-bit mantissa.

The datapath trick. A double-precision multiply produces a 106-bit product. In a non-fused unit, you throw away 53 of those bits before adding. In an FMA, you keep them. The adder is 3× wider than a regular FP adder — it has to align C (a 53-bit mantissa) against a 106-bit product, which means the alignment shifter can shift by up to 161 positions. To hide that latency, FMA units run the alignment of C in parallel with the multiplication of A×B, since the exponents are known immediately.

Why it matters:

• Accuracy: Computing sqrt(x² + y²) the naive way loses precision when x and y are nearly equal in magnitude. With FMA, you can implement Kahan's algorithm to get correctly-rounded results.
• Throughput: Every dot product, matrix multiply, polynomial evaluation, and Horner-form expansion is a chain of multiply-adds. One FMA per cycle beats one multiply + one add per two cycles.
• Correctly-rounded division and sqrt: Newton-Raphson iterations converge quadratically, but only if each step is done in extended precision. FMA gives you that for free.

Concrete example — NVIDIA GPUs. Every CUDA core is fundamentally an FMA unit. When you write c = a * b + c in a CUDA kernel, the compiler emits a single FFMA instruction that executes in one cycle at full throughput. A single H100 SM does 128 FP32 FMAs per cycle. That's why GEMM kernels report peak TFLOPS assuming 2 FLOPs per FMA — the multiply and the add are counted separately even though the hardware does them in one operation.

Rule of thumb: An FMA unit is roughly 1.4× the area of a separate multiplier + adder (mostly the 161-bit alignment shifter and the wider carry-propagate adder), but delivers 2× the throughput on multiply-add-heavy workloads. That area/throughput ratio is why every modern FPU — x86 (since Haswell), ARM (since v8), RISC-V's F/D extensions, GPUs — is FMA-first, with plain multiply and add implemented as FMA with a hardwired zero.