2026-06-28
Imagine you're designing a redundant power system: two synchronous buck converters feed the same 1.2 V rail to a server FPGA. One is running, the other is on standby. When the standby unit starts up, it sees the rail already sitting at 1.2 V — held there by its partner. What happens next determines whether your board survives the next ten seconds.
A naive synchronous buck converter will start its PWM at zero duty cycle and ramp up. But with a low-side MOSFET that switches ON during the first dead-time interval, the output capacitor (already charged by the other supply) dumps current backward through the inductor into the low-side FET. The inductor current goes negative, the high-side body diode can conduct on the next cycle, and you get a brutal output droop — sometimes pulling the rail below regulation and resetting the load. In worst cases, the reverse current trips overcurrent protection or damages the FETs.
The solution is pre-bias startup (also called "monotonic startup"). The controller must detect that the output is already above zero and behave like a diode-rectified converter until its internal soft-start ramp catches up to the actual output voltage.
Two common implementations:
Quick design check: If your soft-start time is tss = 2 ms and your output cap is 100 µF charged to 1.2 V pre-bias, the maximum allowable reverse current to keep droop under 50 mV is roughly:
Irev,max = C × ΔV / Δt = 100 µF × 50 mV / 2 ms = 2.5 mA
That's a tiny budget — far less than the inductor ripple current of a typical 5 A converter (~1 A peak-to-peak). Without pre-bias support, you'd blow that budget on the first switching cycle.
When selecting controllers, look for datasheet keywords: "pre-bias startup," "monotonic startup," "diode emulation during soft-start," or "non-inverting startup." Parts like the TI TPS54620, LM27402, and Analog Devices LTC3833 explicitly handle this. Don't trust a generic synchronous buck controller — many older designs silently fail this test.
