Cornell's ECE 5760 course consistently produces some of the most interesting student FPGA work on YouTube, and this project — by Edwin Chen, Amber Li, and Kyle Mui — is a strong example of why hardware acceleration matters. Procedural landscape generation is computationally expensive: terrain heightmaps typically rely on layered Perlin or simplex noise, with each pixel requiring multiple noise octaves, interpolation steps, and gradient calculations. Running this on a CPU is serial and slow; an FPGA lets you compute many pixels in parallel and pipeline the noise math at the hardware level.

What makes the ECE 5760 final projects worth watching is that students are forced to defend their architectural choices on camera. You typically see a block diagram of the datapath, a discussion of fixed-point vs. floating-point tradeoffs, how memory bandwidth was managed (often the real bottleneck on a DE1-SoC), and a side-by-side speedup comparison against an HPS/ARM software baseline. For anyone learning Verilog or System Verilog, these demos are a good way to see how textbook concepts — pipelining, parallelism, BRAM usage, VGA output timing — actually compose into a working system.

The project webpage referenced in the description is also worth visiting; the ECE 5760 site hosts full writeups with source code, which is rare for student work at this level.