A PLL generates a clock by integrating phase error into frequency — a second-order feedback loop with a VCO at its core. That loop can ring, overshoot, and accumulate jitter cycle after cycle. A DLL solves a narrower problem with a simpler structure: it doesn't generate a new clock, it delays an existing one until its edges line up where you want them.

The architecture: a voltage-controlled delay line (VCDL) — a chain of current-starved inverters or pass-gate stages — sits between input clock and output. A phase detector compares the input edge to the delayed output edge. A charge pump drives a loop filter capacitor, which sets the control voltage that adjusts each stage's delay. Lock occurs when total delay equals exactly one (or N) full clock periods, putting input and output edges on top of each other.

The critical difference from a PLL: the DLL has no integrator in the forward path. It's first-order, unconditionally stable, and — most importantly — does not accumulate jitter. If the input clock has cycle-to-cycle jitter of 5ps, the output has the same 5ps. A PLL, by contrast, integrates phase error over its loop bandwidth and can amplify low-frequency jitter while filtering high-frequency jitter.

The trade-off: a DLL cannot multiply frequency. Output frequency equals input frequency, period. It can only shift phase. It also has a finite lock range — set by the min/max delay of the VCDL.

Real example: DDR3/DDR4 read capture. When the DRAM sends data, it sends a strobe (DQS) edge-aligned with the data. The controller needs DQS shifted 90° (a quarter cycle) so its rising edge falls in the center of the data eye. A DLL with a tap selector picks the delay that produces a 90° shift — one quarter of the period, regardless of frequency. At 800 MHz (1.25 ns period), that's 312 ps; at 1600 MHz, 156 ps. The DLL tracks frequency and voltage automatically.

Rule of thumb — lock range: if each delay stage contributes T_stage picoseconds and the line has N stages, total delay ranges from T_stage (one stage active) to N·T_stage. For lock at clock period T_clk, you need T_stage ≤ T_clk ≤ N·T_stage. Example: 32 stages at 40-80 ps each → lock range roughly 80 ps to 2.5 ns, covering 400 MHz to 12 GHz. If the input falls outside this range, the DLL rails — drives to min or max delay and gets stuck (a real failure mode called "false lock").

FPGAs use DLLs (Xilinx calls them DCMs/MMCMs in older parts) for clock deskewing — compensating for global buffer insertion delay so the on-chip clock arrives in phase with the board clock.