Every MOSFET has four terminals, not three. Software engineers learn about gate, source, and drain — but there's a fourth: the body (or bulk). Normally it's tied to the supply rails and forgotten. But if you can control its voltage independently, you gain a knob that lets you tune transistor behavior after the chip is already manufactured.

The physics: a MOSFET's threshold voltage V_T depends on the voltage between source and body (V_SB). This is the body effect. For an NMOS transistor:

• Forward body bias (FBB): Pull the body slightly above its normal rail (e.g., +200mV). V_T drops, transistor switches faster, but leakage current increases exponentially.
• Reverse body bias (RBB): Pull the body slightly below its normal rail (e.g., -200mV). V_T rises, transistor switches slower, but leakage drops dramatically.

The rule of thumb: V_T shifts roughly 50-100 mV per volt of body bias, depending on process. At advanced nodes (FD-SOI especially), the sensitivity can hit 85 mV/V — letting you trade ~20% performance for ~10x leakage reduction.

Real-world example: STMicroelectronics' 28nm FD-SOI process exposes body bias as a first-class design knob. Mobile SoCs using it apply forward bias during compute bursts (faster CPU, accept the leakage hit for milliseconds) and reverse bias during idle (slower wakeup latency, but standby power drops 5-10x). Renesas and ST microcontrollers use this to hit microamp-level sleep currents while still hitting hundreds of MHz when awake.

Why this is hard: The body forms a parasitic diode with the source. If you forward-bias too aggressively (more than ~500mV typically), that diode turns on and you get massive current through what should be an insulating junction — potentially latchup, where a parasitic SCR locks on and destroys the chip. So body bias generators need careful clamps and are typically driven by on-chip charge pumps with current limiters.

Quick calculation: If your process has body factor γ = 0.4 V^½ and you apply V_SB = -0.3V (reverse bias on NMOS), the V_T shift is approximately:

ΔV_T ≈ γ × (√(2φ_F + |V_SB|) - √(2φ_F)) ≈ 0.4 × (√1.0 - √0.7) ≈ 65 mV

That 65mV shift cuts subthreshold leakage by roughly 10× (since leakage is exponential in V_T/V_T,thermal with V_T,thermal ≈ 26mV at room temp).

This is why modern chips have separate power domains for n-well and p-well voltages — they're not just decoupling, they're tuning knobs the firmware can twist in real time.