22 newsletters today.
Abandoned Futures
2026-08-31
In 1985, a Cambridge startup called Thinking Machines Corporation shipped a black cube five feet on a side, studded with blinking red LEDs, that contained 65,536 processors. Each was a 1-bit ALU with 4 KB of local RAM, wired into a 12-dimensional hypercube network. It was the CM-1 Connection Machine, and it was Danny Hillis's PhD thesis at MIT turned into a commercial product.
Hillis had noticed something obvious that nobody was building for: the brain has ~10¹¹ neurons operating in parallel, not one Cray processor doing 250 million ops/second serially. His 1985 MIT dissertation and book The Connection Machine argued that data-parallel computing — same operation, thousands of data elements, simultaneously — was the future of everything from vision to physics simulation to what we now call machine learning.
The technical roster was surreal. Richard Feynman spent summers at TMC from 1983 until his death in 1988, personally analyzing the router-chip buffer requirements for the CM-1's hypercube network and deriving the correct queue depths from first principles. Marvin Minsky was a co-founder. Case designer Tamiko Thiel gave the machine its iconic look — the red LEDs weren't decoration; they showed per-processor activity, and Feynman insisted they stay because they made parallelism visible.
The CM-2 (1987) added Weitek floating-point coprocessors and hit 28 GFLOPS. The CM-5 (1991) pivoted to MIMD with SPARC nodes and vector units — a 1,024-node configuration cracked 65 GFLOPS on Linpack, briefly the fastest computer on Earth. The CM-5's fat-tree tower with red LED panels was so photogenic it played the InGen supercomputer room in Jurassic Park (1993). Los Alamos, NSA, and NCSA bought them for weather, cryptanalysis, and fluid dynamics.
Then it collapsed. On August 15, 1994, Thinking Machines filed Chapter 11. The kill chain:
Sun bought the software group in 1996 for ~$16 million. The hardware line simply ended.
Why the Connection Machine deserves a second look in 2026: every argument Hillis made in 1985 turned out to be correct. An NVIDIA H100 is 16,896 CUDA cores doing SIMT data-parallel execution — architecturally, it's a CM-2 on a single die. A Cerebras WSE-3 has 900,000 cores on one wafer — that's a CM-1 you can hold in your hands. CUDA kernels are C* with different syntax. JAX's pmap is CM Fortran's FORALL. Transformer training is exactly the "connectionist" workload Hillis built the machine to accelerate.
What we lost wasn't the hardware — silicon caught up. We lost the programming culture. TMC's languages made data parallelism first-class; today's CUDA is grafted onto C++ and leaks abstractions everywhere. A modern Connection Machine — wafer-scale silicon plus a *Lisp-style host language plus visible per-core activity indicators — would be the honest AI accelerator we keep pretending we have.
ArXiv Paper Digest
2026-08-31
Smart contracts — the little programs that run on blockchains like Ethereum and manage billions of dollars in digital assets — have a transparency tradition. To prove they're not doing anything sneaky, projects publish their source code on public block explorers and cryptographically verify that this source matches the compiled bytecode actually running on-chain. For years, this openness has been considered a security feature: anyone can audit the code before trusting it with their money.
This paper argues that openness has quietly become a liability. The reason is LLM agents. Attackers can now point a language-model-driven scanner at every verified contract on a blockchain and, in bulk, hunt for exploitable bugs at a scale no human auditor could match. The very thing that lets defenders inspect code also lets automated adversaries triage the entire ecosystem for prey.
The authors' response is clever, and a little counterintuitive: instead of hiding source code (which would break trust), they propose poisoning the source that gets published so that LLM scanners get confused, while human readers and the actual on-chain bytecode remain unaffected. Think of it as camouflage that only fools machines.
Concretely, they build a defense that:
The key insight is that LLMs and humans read code very differently. LLMs are pattern-matchers that get anchored on surface-level cues (function names, control-flow shapes, familiar idioms). Humans reason about intent and follow data flow. That gap creates room for defensive transformations that are adversarial to LLMs specifically — a new twist on the older idea of adversarial examples, but applied to code understanding instead of image classification.
The broader takeaway is a shift in how we should think about the smart contract disclosure model. When your adversary can afford to LLM-scan every contract ever deployed, "security through transparency" needs new machinery. The paper is an early attempt to give defenders a knob that doesn't require abandoning verifiability altogether.
Daily Automotive Engines
2026-08-31
When a starter grinds, whines, or clicks without cranking, the flywheel ring gear teeth carry a written record of what went wrong. Every engagement leaves a mark, and reading those marks tells you whether the starter drive is failing, the pinion is misaligned, or the engine is stopping in the same position every time.
The three classic wear patterns:
Real-world example: BMW N20 and N26 engines are famous for ring gear failure at 60-80k miles specifically because of stop/start. The engine consistently parks near TDC on cylinder 1, and after roughly 30,000 auto-start cycles the localized teeth strip. BMW's fix was a software update that randomized the stop position across two or three crank angles to spread the wear.
Rule of thumb for pinion-to-ring-gear clearance: the tip of the starter pinion should sit 1.5 to 2.0 mm from the ring gear tooth root when disengaged. Too close and it drags; too far and the pinion doesn't fully mesh before the motor spins up. Measure by pressing a strip of solder between pinion and ring gear, cranking the pinion by hand until it engages, then measuring the crushed thickness. If you're outside spec, add or remove starter mounting shims — typically 0.5 mm per shim.
When diagnosing, always rotate the crank and inspect the entire ring gear. Localized damage on an otherwise-perfect ring is a system problem, not a starter problem.
Daily Debugging Puzzle
stdout Buffering Trap: The Debug Log That Vanishes Right Before the Crash2026-08-31
A junior on your team is chasing a segfault in a batch record processor. They added a printf to trace which record trips the crash, then ran the tool in production redirected to a log file. The tool crashes as expected — but the log is empty. Nothing. Not even the records that processed cleanly.
#include <stdio.h>
int process_record(const char *record) {
printf("processing: %s\n", record);
// ... expensive parsing, validation, DB writes ...
if (record[0] == 'X') {
int *p = NULL;
return *p; // triggers SIGSEGV
}
return 0;
}
int main(int argc, char **argv) {
for (int i = 1; i < argc; i++) {
process_record(argv[i]);
}
return 0;
}
Interactive run: ./proc A B X C prints three "processing:" lines before the crash. Perfect. Piped run: ./proc A B X C > run.log 2>&1 → run.log is zero bytes. The junior swears the printf is being skipped. It isn't.
C's stdio buffering mode depends on what stdout is connected to, decided once at program start. When stdout is a terminal (TTY), it's line-buffered — every \n flushes. When stdout is a file, pipe, or anything non-interactive, it's fully block-buffered (typically 4 KiB or 8 KiB). Three short "processing:" lines don't come close to filling the block.
Normal program exit calls exit(), which runs registered handlers that flush all open FILE* streams. But SIGSEGV — or any signal that causes abnormal termination — skips that. The process dies; the buffered pages in userspace never make it to write(2). Your logs die with the process.
This is the "why did my debug output vanish exactly when I needed it most?" trap. The very act of redirecting to a file to preserve the output is what makes it disappear. Same code, same input, same crash — the presence or absence of a TTY silently changes the buffering discipline, and a null-pointer dereference erases everything you were counting on to diagnose it.
It gets worse under process supervisors (systemd, Docker, Kubernetes) where stdout is always a pipe. Local development "works." Production loses the last N seconds of every crash log.
Force line buffering (or no buffering) at startup, before any output:
int main(int argc, char **argv) {
setvbuf(stdout, NULL, _IOLBF, 0); // line-buffered regardless of destination
setvbuf(stderr, NULL, _IONBF, 0); // stderr is unbuffered on TTY but not pipes
for (int i = 1; i < argc; i++) {
process_record(argv[i]);
}
return 0;
}
Options ranked from safest to most invasive:
setvbuf(stdout, NULL, _IOLBF, 0) — line-buffered; cheap, matches TTY behavior. Best default for logging.setvbuf(stdout, NULL, _IONBF, 0) — unbuffered; every character is a syscall. Fine for low-volume logs, wasteful for hot loops.fflush(stdout) after each meaningful log — surgical, but easy to forget.stdbuf -oL ./proc — no code change, but relies on the operator remembering.Also install a signal handler for SIGSEGV/SIGABRT that calls fflush(NULL) (flushes all streams) before re-raising — belt-and-braces for the crashes you didn't anticipate.
Daily Digital Circuits
2026-08-31
A single-threaded pipeline spends most of its life waiting. A load misses in L1 and stalls for 12 cycles. A branch mispredicts and flushes 15 stages. The ALU sits idle while the front-end refetches. Barrel processors — also called fine-grained multithreaded or interleaved multithreaded processors — solve this by rotating through N hardware threads, issuing one instruction from a different thread every single cycle.
The trick: if you have N threads and a pipeline depth of N stages, no two instructions in flight belong to the same thread. That means zero data hazards, zero control hazards, and no forwarding network needed. The barrel rotates like a revolver's cylinder — thread 0 issues at cycle 0, thread 1 at cycle 1, and by the time thread 0 comes back around, its previous instruction has fully retired. Register file reads never conflict with writes because they happen in different threads.
The cost: single-thread performance is 1/N of a normal pipeline. A 4-thread barrel with a 4-stage pipe gives each thread one instruction every 4 cycles. But if your workload is I/O-bound or memory-bound, the barrel keeps the datapath 100% utilized while a conventional core would be stalled.
Real-world example: The XMOS xCORE family uses 8-way barrel threading. Each thread gets a guaranteed slot every 8 cycles, giving deterministic sub-microsecond response times — that's why xCORE chips are used for software-defined I/O (USB, Ethernet PHY bit-banging) where a normal MCU with interrupts would jitter. Sun's UltraSPARC T1 "Niagara" used 4-way fine-grained threading per core across 8 cores, targeting web-server workloads that spent 75% of their time waiting on memory. Modern GPU warp schedulers are barrel processors at heart — NVIDIA SMs round-robin between ready warps every cycle to hide the 400+ cycle latency of global memory.
Rule of thumb: A barrel with N threads perfectly hides latency up to N cycles. Beyond that, threads start stalling on each other. So if your worst-case load latency is L cycles, you need N ≥ L threads to keep the pipeline full — which is why GPUs run 32+ warps per SM to hide DRAM latency of hundreds of cycles.
Contrast with simultaneous multithreading (SMT / hyperthreading): SMT issues from multiple threads in the same cycle to fill unused issue slots in a superscalar core. Barrel threading issues from one thread per cycle but rotates. SMT preserves single-thread speed; barrels sacrifice it for determinism and simplicity.
Daily Electrical Circuits
2026-08-31
Look at the datasheet for any microcontroller with an XTAL1/XTAL2 pin pair and you're looking at a Pierce oscillator. It's the dominant crystal oscillator topology in digital ICs because it needs exactly one active device (an inverting amplifier), two load capacitors, and a crystal. No transformer taps, no inductor selection, no tricky biasing — just three passives around an on-chip inverter.
How it works: An inverting amplifier (CMOS inverter or common-emitter stage) provides 180° of phase shift. The crystal, operated slightly above its series resonance in the inductive region, combines with the two load capacitors (CL1 and CL2) to form a pi network that adds the remaining 180°. Total loop phase = 360°, loop gain ≥ 1, and Barkhausen is satisfied. The crystal's massive Q (10,000 to 100,000+) forces oscillation onto exactly one frequency.
Load capacitance is the design parameter that matters. The crystal is specified for a particular load capacitance (typically 8, 12, 18, or 20 pF). Miss it and your frequency will be off by 10–100 ppm — enough to break USB, mess up UART timing, or drift a real-time clock by minutes per day.
The load cap formula:
Worked example: A 16 MHz crystal specified for CL = 18 pF, with 4 pF of estimated stray capacitance. CL1 = CL2 = 2 × (18 − 4) = 28 pF. Round to standard 27 pF NP0/C0G ceramics. Never use X7R here — its capacitance varies with voltage and temperature, which detunes your oscillator.
The series resistor Rs: On the drive-side pin (between inverter output and crystal), add a series resistor equal to roughly the crystal's impedance at resonance — typically 1 kΩ for 32.768 kHz watch crystals, dropping to 0–330 Ω for MHz-range crystals. This limits drive power and prevents crushing the crystal, which can crack quartz or shift frequency permanently. Check the crystal's drive level spec (usually 100 µW max for tuning-fork, 500 µW for AT-cut).
Real-world failure: A common Arduino clone bug — the 16 MHz crystal starts but drifts 200 ppm high. Cause: designer used 22 pF caps from a reference design intended for a 12 pF crystal, without checking the actual crystal's CL spec. Fix: measure the crystal, recalculate, swap caps.
Daily Engineering Lesson
2026-08-31
A suspension bridge does something almost paradoxical: it spans thousands of feet using structural elements that have zero bending stiffness. The main cables are just bundled steel wires — they can't resist a moment at all. Yet they carry the entire deck load. The trick is that a cable in pure tension, loaded uniformly along its horizontal span, naturally takes the shape of a parabola. (An unloaded cable hanging under its own weight forms a true catenary — cosh(x) — but once the deck load dominates, the shape is parabolic. Engineers usually design to the parabolic approximation.)
The load path is beautifully linear: deck → vertical suspenders → main cable → tower tops → anchorages. Everything above the deck is in tension. The towers see almost pure vertical compression, because the cable tensions on both sides pull them symmetrically inward and the horizontal components cancel. The anchorages — massive concrete blocks buried in bedrock — resist the horizontal pull of the cable at each end. On the Golden Gate, each anchorage weighs about 60,000 tons.
The key geometric parameter is the sag-to-span ratio (f/L). Typical values are 1/10 to 1/12. For a uniformly distributed load w across span L with mid-span sag f, the horizontal cable tension at any point is:
The maximum tension (at the tower) is H / cos(θ), where θ is the cable angle at the tower. Rule of thumb: a shallower sag means a lighter, cheaper deck but dramatically higher cable tension and anchorage forces. Halve the sag, double the cable tension. That's why designers don't just make cables taut — the anchorages would become impossibly expensive.
Worked example: A 1000 m span carries 200 kN/m of dead + live load, with sag = 100 m (f/L = 1/10). Horizontal tension H = (200 × 1000²) / (8 × 100) = 250,000 kN. That's 25,000 tons of horizontal pull the anchorage must resist — forever, on both sides.
The other subtle failure mode is aerodynamic instability. Tacoma Narrows (1940) taught engineers that a slender, torsionally flexible deck can couple with wind to produce self-exciting oscillations (flutter). Modern suspension decks use deep trusses or aerodynamically shaped box girders (Great Belt, Akashi Kaikyō) tested in wind tunnels. The main cable itself is stable; the deck is what dances.
Compare to cable-stayed bridges: stays run straight from tower to deck, putting the tower in bending as well as compression, but eliminating the anchorage. That's why cable-stayed dominates the 300–1000 m range and suspension dominates above 1000 m — anchorage cost gets amortized only over very long spans.
Forgotten Books
2026-08-31
Book: A Journal of Natural Philosophy, Chemistry, and the Arts [aka "Nicholson's Journal"] (November, 1806) by William Nicholson (London) (1806)
Read it: Internet Archive
In November 1806, William Nicholson's Journal of Natural Philosophy, Chemistry, and the Arts published the concluding installment of a remarkable paper by Benjamin Thompson, Count Rumford: "Experiments and Observations on the Adhesion of the Particles of Water to each other." Buried in the dry prose is a genuinely astonishing observation — Rumford had figured out surface tension by dropping mercury onto liquids and watching what happened.
Mercury is 13.5 times denser than water. A droplet of it has no business floating. And yet Rumford noticed that tiny mercury spherules, released carefully onto water, would sit on the surface as if resting on a taut membrane. When he switched the water for ether, the same droplets plunged straight through:
"The very smallest spherules of mercury which I let... appears to fall through this liquid, seldom failed to mix immediately with the mass of mercury on arriving at its surface, where they entirely disappeared; and I have never succeeded in causing either a spherule of mercury, or the smallest metallic particle, nor any other body of greater specific gravity than ether, to swim upon its surface."
Rumford's interpretation was startlingly modern. He proposed that liquids form a "kind of film" at their surface whose "force" depends on how strongly the particles of the liquid adhere to each other. Water's particles cling tightly, so the film is strong enough to hold mercury. Ether's particles barely hold onto each other, so its film is feeble.
Then he closed the loop with a second insight that we still teach today:
"It is known that ether evaporates very rapidly. Is not this another proof that the particles of this liquid adhere to each other with much less force than those of water?"
He had connected surface tension, intermolecular cohesion, and evaporation rate as three faces of the same underlying phenomenon — the strength of the forces between the particles of a liquid. This is essentially the modern picture. Weak intermolecular forces mean low surface tension AND high vapor pressure. Rumford didn't have molecules in the modern sense, and he didn't have thermodynamics, but he had the physical intuition dead right.
The formal mathematical theory of surface tension was being developed at almost the exact same moment by Thomas Young (1805) and Pierre-Simon Laplace (1806). Rumford's contribution — arriving via a bellows, a glass of mercury, and a droplet — is a beautiful reminder that the great discoveries of surface physics didn't come from equations first. They came from someone patient enough to notice that a heavy metal droplet was doing something impossible.
You can replicate his experiment tonight. A steel sewing needle, laid gently on the surface of a glass of water, will float — the same "film" Rumford identified holding it up. Add a drop of dish soap (which shreds the film by disrupting cohesion) and it sinks instantly. Two hundred and twenty years later, the demonstration still works.
Forgotten Darkroom
2026-08-31
Book: COLOR FILM/PRINT DRYER STUDY -- STAFF STUDY by CIA Reading Room (1966)
Read it: Internet Archive
Buried in a declassified 1966 staff study from the CIA's National Photographic Interpretation Center (NPIC) is one of the most delightfully mundane bottlenecks in Cold War intelligence: the spies couldn't dry their photos fast enough.
The problem, laid out with bureaucratic precision:
The automatic color processing equipment in NPIC/PSD can process Sheet film or color paper at the rate of 200 8" x 10" sheets or equivalent each hour... The dryer cabinets for film, which can handle about 60 sheets per hour, cannot handle the output of automatic color processing equipment.
Even more remarkably, the study confesses that money could not solve the problem:
There are no high quality, rapid color film or color paper dryers commercially available that will solve the drying requirement of the color sheet material produced in NPIC.
The forgotten context: NPIC was the agency that interpreted imagery from U-2 flights, CORONA satellites, and other overhead reconnaissance. The study notes that "on every mission, NPIC prepares color viewgraphs showing the flight path of the mission. Normally, more than 50 viewgraphs each of several tracks are prepared for each mission." Analysts were physically waiting on wet photographs to review Soviet missile sites and Vietnam-era targets.
The drying process itself was surprisingly craft-like. Glossy prints were pressed emulsion-side against a "highly polished chromed surface, usually a drum" — a technique called ferrotyping that produced the mirror-shiny finish anyone who owned family photos before the 1990s will remember. Film hangers were dangled in hot-air cabinets while technicians prayed against "watermarks, abrasions, scratches, image distortion, peeling, curl, fading, color shifts, mottling, etc."
Why this is a lost world: Today, an intelligence analyst pulls up a satellite image on a monitor in real time. In 1966, the intelligence cycle was gated by the drying rate of gelatin emulsion. The most sophisticated surveillance apparatus on Earth was being throttled by a physical property of wet paper.
What makes this document quietly prophetic is that it identifies exactly the kind of problem that would eventually kill film photography altogether. The CIA wasn't just fighting the Soviets — they were fighting Kodak's chemistry. Every improvement in cameras, lenses, and processing chemistry made the drying bottleneck worse. There is a straight line from this 1966 memo to the CIA's later investments in digital imaging (KH-11 KENNEN, launched 1976, was the first electro-optical reconnaissance satellite that beamed images down without film at all).
The modern parallel: This is the 1960s equivalent of your GPU being fast enough to render 240fps but your monitor only doing 60Hz. Or an LLM that can generate tokens faster than the network can stream them. The pattern — a downstream physical constraint bottlenecking an otherwise-optimized pipeline — is the eternal story of engineering. The CIA's answer was to invent a better dryer. The industry's answer, ultimately, was to stop drying anything.
Forgotten Patent
2026-08-31
In 1959, Robert Noyce and Jack Kilby raced to file the integrated circuit patents that history remembers. But neither IC could have been manufactured at scale without a quieter filing that same year by their Fairchild colleague, a Swiss-born physicist named Jean Amédée Hoerni. His patent — US 3,025,589, "Method of Manufacturing Semiconductor Devices," filed May 1, 1959 — described the planar process, the fabrication technique that every silicon chip on Earth still uses today.
The problem it solved. Before Hoerni, transistors were built as "mesas": tiny volcano-shaped islands etched up out of a silicon wafer, with the fragile p-n junctions exposed to air on the sloped sidewalls. Dust, moisture, and stray ions crept in and killed devices unpredictably. Yields were miserable. Bell Labs, Texas Instruments, and Fairchild all struggled with the same phantom failures.
Hoerni's insight. Silicon, when heated in oxygen, grows a glassy skin of silicon dioxide — SiO₂ — that is chemically inert, electrically insulating, and stunningly good at blocking the very impurities that ruined mesa transistors. Hoerni proposed leaving that oxide layer on the wafer, cutting precise windows through it with photolithography, diffusing dopants through the windows, and then re-covering everything with more oxide. The junctions ended up buried beneath a protective glass shield, and the entire top surface was flat — planar. Metal wires could then be evaporated across the surface to connect devices.
Why it changed everything. Three things fell out of Hoerni's flat surface, all at once:
The straight line to 2026. Every step in a modern fab — 3nm FinFETs at TSMC, 3D NAND stacks at Samsung, the M-series chips in your laptop, the H-series GPUs training frontier models — is a lineal descendant of Hoerni's 1959 recipe. Grow oxide. Pattern it. Diffuse (now implant) through the windows. Cover it up. Repeat, now sixty-plus times per wafer. When EUV lithography machines from ASML print features 5 nanometers wide, they are still printing onto a planar surface, still using oxide as a mask, still relying on the passivation trick Hoerni sketched in his lab notebook in December 1957.
The recognition gap. Kilby won the 2000 Nobel Prize. Noyce co-founded Intel and became a legend. Hoerni left Fairchild in 1961 as one of the "Traitorous Eight," co-founded Amelco, Union Carbide Electronics, Intersil, and later devoted his fortune to building schools for the Balti people in northern Pakistan. He died in 1997, largely unknown outside chip-fab circles — despite having invented the manufacturing process that made the entire semiconductor industry, and by extension the digital economy, physically possible.
Daily GitHub Zero Stars
2026-08-31
Language: Go
tailnats is one of those elegantly-scoped projects that makes you think "of course somebody should have built this." It bundles a NATS JetStream message broker together with Tailscale's tsnet library into a single self-contained Go binary. The result: a message broker that joins your tailnet directly as a node, reachable at a MagicDNS name, with WireGuard-based auth and encryption baked in — no separate networking layer to configure, no TLS certs to rotate, no exposed public ports.
Why is this interesting? NATS is already famously lightweight and fast, and JetStream adds durable streams, key-value stores, and object storage on top. But deploying it securely across multiple hosts, clouds, or homelab environments usually means dealing with TLS, mTLS, firewall rules, and often a reverse proxy. By embedding tsnet, the broker becomes a first-class citizen of your tailnet — any device authorized on your Tailscale network can reach it as if it were on the LAN, and ACLs can gate access at the identity layer rather than the network layer.
This is particularly appealing for:
The single-binary distribution model also makes it a plausible fit for small on-prem deployments where operational simplicity beats horizontal scalability. It's the kind of building block that could quietly become a favorite for anyone tired of Kubernetes-scale answers to homelab-scale problems.
Daily Hardware Architecture
2026-08-31
The uop cache (Decoded Stream Buffer, DSB) stores decoded micro-ops so the CPU can skip the expensive x86 length-decode and translate stages. But its slots have fixed-width encoding constraints, and x86 instruction prefixes eat into that budget in ways that surprise even experienced developers.
Each DSB entry on Intel Skylake-family cores can hold up to 6 uops per 32-byte fetch window, but the encoding also has to store the original instruction pointer offset, immediate operands, displacement bytes, and any prefix bytes. When an instruction carries multiple prefixes — REX for 64-bit operand size, VEX for AVX encoding, EVEX for AVX-512, plus segment overrides or LOCK — the metadata overhead can push the instruction into a form that won't fit in a DSB slot at all. The instruction then falls back to the legacy decode path (MITE), and the whole 32-byte window may be evicted from the uop cache.
Concrete example: a hand-written crypto loop using AVX-512 with EVEX prefixes, masking ({k1}), and memory broadcasts ({1to8}) can carry 4-byte EVEX prefixes plus a 32-bit displacement. Intel's optimization manual documents that instructions requiring the MSROM path, or those with multi-byte immediates plus multi-byte displacements plus prefixes, may not enter the DSB. A tight AVX-512 loop that should run entirely from the uop cache at 6 uops/cycle instead falls back to legacy decode at ~4 uops/cycle from the complex decoder — a 33% frontend bandwidth loss on code that looks maximally optimized.
Rule of thumb: if an instruction has both an immediate operand (say, 32-bit) and a memory operand with a 32-bit displacement and a prefix, it consumes roughly:
That's 3 of your 6 slots for a single instruction. Two such instructions and the DSB line is full — you get 2 instructions per 32-byte window instead of 6, cutting effective frontend throughput by 3x.
Practical mitigation: use perf stat -e idq.dsb_uops,idq.mite_uops to see the DSB-to-MITE ratio. If MITE uops climb above ~10% of total, hunt for instructions with big immediates + big displacements + VEX/EVEX prefixes. Fixes: use register-indirect addressing, hoist constants into registers, or prefer VEX (3-byte) over EVEX (4-byte) when AVX-512 features aren't needed.
Daily Low-Level Programming
2026-08-31
Standard TCP requires a three-way handshake (SYN, SYN-ACK, ACK) before either side can send application data. That's one full round-trip time (RTT) of latency before your HTTP GET even leaves the wire. For a mobile client to a data center 80ms away, you've paid 80ms before the server sees a byte of the request.
TCP Fast Open (TFO, RFC 7413) lets a client piggyback data in the SYN packet on repeat connections. The trick is a cryptographic cookie that proves the client owns its source address, preventing amplification attacks.
The flow:
TCP Fast Open Cookie Request option. Server generates a cookie (typically AES-encrypting the client's IP with a server-side key) and returns it in the SYN-ACK. Normal handshake completes.Enabling it:
sysctl net.ipv4.tcp_fastopen=3 (bit 0 = client, bit 1 = server).setsockopt(fd, SOL_TCP, TCP_FASTOPEN, &qlen, sizeof(qlen)) before listen().sendto() with MSG_FASTOPEN instead of connect()+send(), or set TCP_FASTOPEN_CONNECT on the socket and let the kernel defer the SYN until the first write().Real-world example: Google measured TFO cutting page-load times by 4–41% for Chrome-to-Google-frontend connections, with larger gains on high-latency mobile networks. The savings scale directly with RTT — every connection saves exactly one round trip.
Rule of thumb: TFO saves one RTT per repeat connection. If your service does 10 short-lived HTTPS connections to a 100ms-away server, TFO shaves ~1 second off total latency (though TLS 1.3 0-RTT stacks on top and matters more for encrypted traffic).
Gotchas:
RFC Deep Dive
2026-08-31
For nearly two decades, the rule "check that the certificate matches the hostname" was folklore. Every protocol — HTTPS, SMTP over TLS, IMAP, XMPP, LDAP — reinvented the wheel, and each one did it slightly differently. RFC 6125 finally wrote down, in one place, what "matches" actually means. It is the reason your TLS library rejects *.example.com for foo.bar.example.com, and why CN= is quietly being retired.
The problem it solves. RFC 2818 (HTTPS) gave rough guidance for browsers in 2000. RFC 2830 said something else for LDAP. RFC 3207 for SMTP was vague. XMPP had its own rules involving id-on-xmppAddr. Implementers had to synthesize half a dozen specs — and got it wrong. Notorious bugs like the null-byte CN attack (Moxie Marlinspike, 2009), where a cert for www.paypal.com\0.evil.com matched www.paypal.com in naive C string comparisons, showed the cost of ambiguity. RFC 6125 tries to unify the rules and close these holes.
Key design decisions.
CN field of the certificate Subject was never meant to hold DNS names — it was a human-readable label. RFC 6125 says clients MAY fall back to CN but only if no subjectAltName (SAN) of type dNSName is present. Modern clients (Chrome since 58, most libraries) now reject CN outright.subjectAltName. The reference identifier the client uses to compare comes from the user or configuration ("the URL bar said mail.example.com"), not from the cert.*.example.com ✓, foo.*.example.com ✗). It matches exactly one label — *.example.com matches a.example.com but not a.b.example.com and not the bare example.com. Partial wildcards like f*.example.com are discouraged, and most clients reject them._xmpp-server.example.com), and URI-ID (a full URI). SRV-ID was a big deal for XMPP and CalDAV, which use SRV records to indirect hostnames.Why it matters today. Every TLS-enabled protocol now cites RFC 6125 by reference instead of writing its own matching logic. When Let's Encrypt issues you a cert, the SAN list follows these rules. When Go's crypto/tls, Python's ssl module, or OpenSSL 1.1.0+'s X509_check_host() validate a hostname, they implement 6125. It also underpins later specs like RFC 7525 (TLS BCP) and RFC 9525 (which replaces 6125 in 2023, tightening wildcards further and formally killing CN fallback).
Quirky history. The document was chaired through IETF by Peter Saint-Andre, who had spent years dealing with XMPP's identity mess. It took over two years of debate — largely about wildcards. Should *.example.com match example.com? (No.) Should * alone ever be valid? (No.) What about internationalized domain names? (Compare A-labels, never U-labels.) The wildcard section alone is nearly a third of the RFC — because that's where every deployed implementation had disagreed.
Daily Software Engineering
2026-08-31
Two-Phase Commit has a nasty failure mode: if the coordinator dies after participants vote YES but before they hear the commit decision, they're stuck. They can't abort (someone might have committed) and they can't commit (someone might have aborted). They hold their locks and wait. Forever, in the worst case. Three-Phase Commit (3PC) was designed to fix exactly this — to make consensus non-blocking when the coordinator fails.
3PC splits the commit into three phases instead of two:
The magic is in the recovery rule: if the coordinator dies, participants can elect a new coordinator and reach a safe decision by themselves. If any participant reached the PreCommit state, the new coordinator commits. If none did, it aborts. No more indefinite blocking.
Real-world example: Imagine a distributed order system booking a flight, hotel, and rental car atomically. In 2PC, if the coordinator crashes right after everyone votes YES, all three services hold locks on inventory. The flight seat, hotel room, and car sit unbookable until someone manually intervenes. In 3PC, once the coordinator sends PRE-COMMIT, any surviving participant can drive the transaction to completion — the seat gets booked or released within seconds of the failure.
Rule of thumb: 3PC costs you 50% more network round trips than 2PC (three phases instead of two). On a system with 10ms inter-node latency, a 2PC transaction takes ~40ms (two round trips) while 3PC takes ~60ms. That's a significant tax for every transaction to protect against a rare failure mode.
Here's the catch nobody tells you: 3PC assumes a synchronous network with bounded message delays. In real networks, a slow participant is indistinguishable from a dead one, and 3PC can produce inconsistent decisions during network partitions. That's why production systems (Spanner, CockroachDB, etcd) use Paxos or Raft instead — they handle partitions correctly and only pay the extra round trip when actually needed.
3PC is a beautiful academic protocol that taught us why consensus is hard, but its assumptions don't hold in production networks.
Tool Nobody Knows
2026-08-31
Backups aren't the only defense against bit rot — and they're expensive if you just want to survive a few flipped bits on a decade-old tarball. par2 (Parchive v2) generates redundancy files alongside your data using Reed–Solomon codes. Feed it 10% overhead and you can rebuild the original after losing up to 10% of the bytes — anywhere in any combination of the covered files, without needing to know in advance which will go bad.
It ships in every distro (apt install par2, brew install par2) and is the same tool Usenet has used for reliable file transfer for two decades.
The basic workflow:
# Create 10% redundancy over a directory of files
par2 create -r10 -n1 archive.par2 *.tar.zst
# Two files result:
# archive.par2 — small index
# archive.vol000+NN.par2 — the actual recovery blocks
# Later, verify integrity (fast — just checks hashes)
par2 verify archive.par2
# Something got corrupted? Repair in place.
par2 repair archive.par2
Where it earns its keep: I've watched par2 repair silently rebuild a 40 GB backup archive that had ~200 MB of bad sectors from a dying SSD, in one command, with no user intervention. md5sum would have told me the file was toast. tar would have bailed halfway through. par2 fixed it.
Useful flags you'll actually want:
-r<N> — redundancy percent. 5% survives casual rot; 10–20% survives serious damage; 100% is a full mirror.-n<N> — number of recovery volumes. -n1 keeps it in one file; -n7 splits so you can spread volumes across media.-s<bytes> — block size. Smaller blocks = finer-grained repair but bigger index. Default (auto) is usually right.-B<dir> — base directory. Necessary when the source files aren't in $PWD.-q / -qq — one q hides progress, two silences almost everything (good for cron).A pattern I use for cold archives on rotating cheap disks:
tar --zstd -cf snapshot-$(date +%F).tar.zst /data
par2 create -q -r15 -n1 snapshot-$(date +%F).tar.zst
# Ship both the .tar.zst and its .par2 companions to two locations.
# If either copy corrupts, either .par2 set can heal it back to original.
Why not just rely on ZFS/Btrfs scrub? Because par2 rides with the file. Move it to a FAT32 stick, upload to S3 Glacier, email it to a colleague, burn it to BD-R — the recovery data travels along. It's format-agnostic and filesystem-agnostic. Cloud storage checksums tell you a file went bad; par2 lets you actually fix it.
Why not sha256 + duplicate copies? Duplicates cost 100% overhead. par2 lets you pick your survivability/cost tradeoff at the byte level, and heals partial damage even when both copies have different corruption — you can feed multiple damaged copies into par2 repair and it will cherry-pick good blocks from each.
Caveat: par2 protects file contents, not filenames, mtimes, or ACLs. Wrap the whole archive in tar first so metadata rides along inside the payload.
What If Engineering
2026-08-31
Imagine a 400-meter tower in Phoenix. Inside: no soil, no pots, no hydroponic trays. Just a vast open volume where mature trees hang suspended, roots dangling into a perpetual indoor fog. This is aeroponics scaled to cathedral proportions — a vertical cloud forest where a saturated aerosol delivers water and nutrients directly to root hairs at 100% humidity, no substrate required.
The physics is real. Aeroponic root zones consistently outperform hydroponics because roots get unlimited O₂ diffusion (air is ~210,000 ppm oxygen vs. ~8 ppm dissolved in water). NASA's aeroponic trials showed 3× faster growth and 98% less water use than field agriculture. Scale it up and you get something interesting.
Take a cylinder 60 m across, 400 m tall — volume ~1.1 million m³. Suspend trees on Kevlar cable trellises anchored to internal ring beams every 20 m. Roots hang bare into the interior. Ultrasonic misters (2.4 MHz piezoelectric transducers, ~5 μm droplets) maintain a fog at 100% RH throughout.
Trees transpire ~2 L/m² leaf area per day. A mature oak has ~600 m² of leaves → 1,200 L/day. Pack the tower with ~2,000 trees at 500 m² average leaf area → 2,000 × 500 × 2 = 2,000,000 L/day of transpiration.
But here's the trick: the tower is sealed. Transpired water rises, hits a chilled ceiling condenser (dew point ~12°C when interior is 25°C/100% RH), condenses, and drips back to the reservoir. Recovery efficiency of a well-designed condenser: ~92%. Net water loss: ~160,000 L/day for 2,000 trees — one-tenth what the same trees would need in an Arizona orchard.
Maintaining 100% RH in a 1.1M-m³ volume is harder than it sounds. At 25°C, saturation is ~23 g/m³ water vapor → the chamber holds ~25 tonnes of vapor at steady state. Refresh rate driven by transpiration + condensation cycle: complete turnover every ~18 minutes. That's a 1,000 kW cooling load on the ceiling coils (latent heat: 2,000,000 L/day × 2,260 kJ/kg ÷ 86,400 s ≈ 52 MW if you condensed all transpiration — realistically closer to 5 MW with partial recovery loops).
Trees weigh ~500 kg each at maturity → 1,000 tonnes hanging load, trivially handled by a steel exoskeleton. The harder problem is light. Trees need ~200 μmol/m²/s PAR minimum. Even with an ETFE-clad tower flooding sunlight in, self-shading means only the outer ~5 m of canopy gets enough. You need internal LED supplementation: at 2.3 μmol/J efficacy, lighting 400,000 m² of canopy interior draws ~35 MW.
Total power: ~40 MW. Total water: 160,000 L/day. Output: a mature carbon-sequestering forest — ~44 tonnes CO₂/year — plus a 25°C oasis microclimate in a 45°C city. The tower itself becomes a passive humidity anchor; leakage humidifies surrounding blocks by 5-8%, dropping outdoor cooling loads measurably.
Cost per tonne CO₂ sequestered: laughable compared to direct air capture. But cost per square meter of usable green space in a desert megacity? Suddenly the numbers get interesting. Singapore's Supertrees hint at the aesthetic. Aeroponic cloud towers push it into biome territory.
Daily YT Documentary
2026-08-31
Channel: Aphano History (0 subscribers)
Caveat: all three candidates today are rough — hashtag-spam titles, a non-English railway doc, and what looks like a Short repurposed as a teaser. This one wins on subject matter alone.
The Poyais scheme is arguably the most audacious financial fraud in history. In the 1820s, Scottish soldier Gregor MacGregor returned from South America claiming to be the "Cazique" (prince) of Poyais, a lush Central American nation on the Mosquito Coast. He printed currency, sold land grants, issued sovereign bonds on the London Stock Exchange, and even wrote a 350-page guidebook — all for a country that did not exist.
Hundreds of Scottish settlers sailed to claim their new homes. What they found was uncleared jungle. Most died of disease and starvation before rescue. Astonishingly, MacGregor evaded serious prosecution and tried variations of the scam for decades afterward.
It's a story that touches on 19th-century capital markets, colonial mania, the credulity of the London bond bubble, and how one charismatic conman exploited every institution meant to prevent exactly this. Even a rough retelling of the Poyais affair is worth 5 minutes of your time — the facts do most of the work.
Daily YT Electronics
2026-08-31
Channel: Emilio Martinez III (800 subscribers)
Verilog simulation is the unglamorous but essential step between writing HDL and actually loading a bitstream onto silicon. Skip it, and you'll spend hours re-synthesizing designs to chase bugs that a five-second testbench would have caught. This tutorial from Emilio Martinez III focuses squarely on that workflow: how testbenches are structured, how you drive inputs into a device-under-test, and how you observe outputs as waveforms or console prints.
What makes this worth the time over the many other "intro to Verilog" videos is the emphasis on simulation as a first-class design activity. Beginners often treat the testbench as an afterthought — a throwaway file to prove the code compiles. But experienced FPGA engineers spend the majority of their time in simulation, not on hardware, because the debug loop is orders of magnitude faster and you can inspect every internal signal.
Expect coverage of the basic testbench skeleton (module with no ports, initial blocks, clock generation), stimulus patterns, and reading waveform output. If Martinez walks through $monitor, $display, and $dumpvars for VCD generation, you'll come away with the toolkit needed to verify any small combinational or sequential design before ever touching a dev board.
Good foundational content from a small channel that clearly wants to teach rather than chase views.
Daily YT Engineering
2026-08-31
Channel: cadtabs (622 subscribers)
Response spectrum analysis gives you a peak modal response for each vibration mode of a structure — but those peaks don't happen at the same instant, so you can't just add them. The modal combination rule you choose is how you reconcile that: it turns a vector of per-mode peaks into a single design value for base shear, drift, or member force. Get it wrong and you either badly under-design (missing coupled-mode interaction) or waste steel chasing a bound that will never occur.
This video walks through the three workhorse rules that every seismic engineer should know cold: ABS (absolute sum — conservative upper bound, assumes all modal peaks coincide), SRSS (square root of sum of squares — assumes modes are statistically independent, valid when natural frequencies are well-separated), and CQC (complete quadratic combination — includes cross-modal correlation coefficients, essential when frequencies are closely spaced, as in 3D buildings with torsional modes near translational ones).
The reason CQC exists at all is the failure mode of SRSS on modern asymmetric buildings: when two modes sit within ~10% of each other in frequency, their responses are correlated, and SRSS silently under-predicts. CQC's cross-terms fix that. Expect the video to cover when each rule is code-permitted (ASCE 7, IS 1893, Eurocode 8 all have opinions), and the physical intuition for why closely-spaced modes need special treatment.
Daily YT Maker
2026-08-31
Channel: David Walton - Woodwork DIY (7760 subscribers)
Most of today's candidates are Shorts, hashtag-spam thumbnails, or Amazon tool listicles — the kind of content that's engineered for the algorithm rather than the workshop. This podcast-style build discussion is the one exception, and it's genuinely worth an hour of your attention.
David Walton walks through his process for building an American Irish armchair — a distinctive vernacular form with turned spindles, a shaped crest rail, and joinery that has to accommodate the compound angles between the seat, back, and arms. Rather than a time-lapse "satisfying" build, this is a slower, reflective breakdown of why he made specific choices: stock selection, sequencing the joinery, dealing with the compound geometry, and the tradeoffs between traditional methods and modern shop shortcuts.
Discussion-format woodworking content is undervalued. You get the reasoning behind the cuts — the failed first attempts, the setup jigs that didn't survive contact with the wood, the moments where a chisel worked better than a router. For anyone considering a chair build, this is the sort of context that keeps you from making the expensive mistakes yourself.
At 7.7k subscribers, Walton sits right at the edge of the small-channel threshold, and his format — talking through a completed build rather than performing one for the camera — is exactly the kind of thing that gets buried under Shorts.
Daily YT Welding
2026-08-31
Channel: TIMBER (2790 subscribers)
This one stands out from a field otherwise dominated by hashtag-spam Shorts and low-effort restoration reuploads. TIMBER walks through the design and fabrication of a 360° rotary gauge for a metal lathe — a genuinely useful shop accessory that lets you index workpieces by angle for drilling, milling, or layout work on round stock.
What makes gauge-making projects like this worth watching is that they force the maker to be more accurate than the tool they're building. Dividing a circle into 360 evenly spaced marks on a manual lathe is a real precision challenge — you're up against backlash in the compound, runout in the chuck, and the limits of your own eye when scribing lines. Expect to see rotary table setup or indexing plate work, careful facing and boring of the dial body, and stamping or engraving of graduations.
For hobby machinists, this is exactly the kind of project that pays back the shop time twice: you end up with a tool you'll actually reach for, and you level up your setup and layout skills in the process. TIMBER's channel is small (under 3k subs) but the project scope and title suggest a proper build video rather than a montage.
