2026-07-13
When you walk across a carpet and touch a doorknob, you can dump 2,000 to 15,000 volts into whatever you touch. That same finger, laid on an IC pin, would obliterate a 1V transistor in nanoseconds. The fact that chips survive this is entirely due to ESD (electrostatic discharge) protection structures — sacrificial devices sitting between every pad and the core logic.
The workhorse is the dual-diode clamp: two diodes on each I/O pad, one to VDD and one to VSS. Under normal signaling they're reverse-biased and invisible. When a pin gets zapped positive, the top diode forward-biases and shunts current into VDD. Negative zaps go through the bottom diode into VSS. A separate power clamp (usually a big NMOS with a trigger circuit) sits between the rails to sink the current so it doesn't back-feed into the core.
The trick is that ESD events happen in nanoseconds, so the protection has to turn on faster than the pulse peaks. A common trigger uses an RC network (~100 ns time constant) that detects a fast dV/dt on VDD and momentarily turns on a massive shunt NMOS — a technique called GCNMOS (gate-coupled NMOS) or RC-triggered rail clamp.
The industry benchmarks come from three test models:
Rule of thumb for the designer: HBM 2 kV through 1.5 kΩ = 1.33 A peak current. Your clamp diodes have to handle over an amp for ~150 ns without melting. That's why ESD diodes are large, use silicided ballast resistors, and often have salicide blocking to spread current across the whole junction instead of concentrating at one spot.
Real-world example: USB-C connectors experience frequent hot-plug ESD. TI's TPD4E02B04 sits between the connector and the SoC, clamping 8 kV HBM in under a nanosecond so the phone's expensive main chip only sees ~5 V transient. The sacrificial part costs pennies; the SoC costs $50.
Every pad you see on a die has a small "ESD device" cell adjacent to it — usually 5-10% of total die area is spent just surviving human contact.