Every out-of-order CPU needs a place to park decoded instructions until their operands are ready. Two architectural choices dominate: reservation stations (Tomasulo-style) and issue queues (modern designs like Intel Skylake and ARM Neoverse). Both solve the same problem — pick ready instructions and fire them — but they store operands differently, and that difference cascades into gate count, power, and clock frequency.

Reservation stations hold the actual operand values. When a producer broadcasts its result on the common data bus, every waiting RS entry compares the result tag against its source tags and, on a match, latches the value into the entry itself. When both operands are present, the entry becomes ready. The value lives in the RS until issue.

Issue queues hold only tags — pointers into a separate physical register file (PRF). Entries track "am I waiting on physical register p42?" with a ready bit per source. When p42 completes, a wake-up bus asserts, matching entries flip their ready bit, and the select logic picks a winner. On issue, the queue reads operands from the PRF then, not before. The value never lives in the queue.

The tradeoff is brutal. Reservation stations need wide storage per entry — two 64-bit operand slots plus tags — so a 60-entry RS burns real silicon and burns power on every CDB broadcast (every entry does a full comparator + latch). Issue queues cut per-entry width to a handful of tag bits and ready bits, so you can build a 97-entry queue (Skylake) in the area of a 40-entry RS. The cost: an extra pipeline stage to read the PRF between select and execute, and a much larger PRF read port count.

Real example: The original Pentium Pro (1995) used reservation stations with 20 entries. Modern Intel Golden Cove uses a unified scheduler of ~97 issue queue entries feeding a PRF with 280+ integer physical registers. The industry moved to issue queues once out-of-order windows grew past ~40 entries because RS area scales as (entries × operand_width) while issue queue area scales as (entries × log(PRF_size)).

Rule of thumb: Wake-up power in a modern scheduler is roughly N × M × C, where N is queue entries, M is wake-up buses (one per issue port), and C is a comparator's switching energy (~5 fJ in 7nm). A 100-entry, 8-wide scheduler dissipates ~4 pJ per cycle just on tag matching — about 5% of total core power at 4 GHz.