2026-08-17
A 6T SRAM cell looks trivially symmetric — two cross-coupled inverters plus two access transistors — but the transistor widths in that cell are the single most-debated numbers in a memory design. Get them wrong and the cell either flips during a read (read-upset) or can't be written at all (write-fail). The knobs are two ratios: beta (cell ratio) and gamma (pull-up ratio).
The cell: Each inverter has a PMOS pull-up (PU) and an NMOS pull-down (PD). An NMOS access transistor (PG, "pass-gate") connects the internal storage node to the bitline. Six transistors total, two of each type.
Why beta matters: On a read, both bitlines are precharged to VDD. The access transistor turns on and tries to pull the "0" storage node up through PG, while PD fights to hold it down. If PG is stronger than PD (low beta), the internal node rises above the inverter trip point and the cell flips. Rule of thumb: beta ≥ 1.5, often 2.0 in high-reliability designs. That's why PD is typically the widest transistor in the cell.
Why gamma matters: On a write, the driver pulls one bitline to ground. PG must overpower PU to drag the "1" node down through the trip point. If PU is too strong (high gamma), the write fails. Rule of thumb: gamma ≤ 1.8, often closer to 1.0. That's why PU is usually the smallest transistor — minimum width.
The squeeze: Both constraints push in opposite directions on PG. Make PG narrow → good read stability (high beta), bad write-ability (high gamma). Make PG wide → good writes, bad reads. Classic Intel/TSMC 6T cells settle around PD:PG:PU ≈ 2:1:1 in width.
Real-world example: When TSMC characterized their 7nm SRAM (~0.027 µm² cell), they published Static Noise Margin (SNM) curves — the "butterfly plot" that shows the largest square you can fit between the two inverter transfer curves during a read. An SNM below ~100 mV at worst-case corner means the cell isn't shippable. Half-VDD read-assist and negative-bitline write-assist circuits exist precisely because at sub-10nm you can no longer satisfy both ratios simultaneously with sizing alone.
Quick check: If your cell fails writes but reads fine, shrink PU or widen PG. If it flips on reads, widen PD or shrink PG. You almost never touch two knobs at once.