Lead Compensation: Adding a Zero to Cancel a Troublesome Pole

2026-06-04

Last lesson we covered dominant-pole compensation — making one pole low enough that the loop crosses unity gain before any other pole adds significant phase. The cost was bandwidth: you throttle gain across the entire useful spectrum just to stay stable. Lead compensation is the surgical alternative. Instead of pushing your dominant pole down, you add a zero right where a troublesome pole lives, locally canceling the phase lag it causes.

Recall that every pole subtracts up to 90° of phase as frequency climbs past it, and every zero adds up to 90°. If your loop has a pole at 100 kHz that's eating your phase margin, dropping a zero at 100 kHz flattens that contribution — the phase dip never happens, and you reclaim bandwidth.

The classic implementation: put a small capacitor Cf in parallel with the feedback resistor Rf of an inverting op-amp. This creates a zero in the noise gain at:

Place this zero at the frequency where your op-amp's open-loop response intersects the closed-loop noise gain — exactly where phase margin is being lost.

Real-world example: You're building a photodiode transimpedance amplifier. The photodiode has 50 pF of junction capacitance, and you've chosen Rf = 1 MΩ for high gain. That Cdiode·Rf combination creates a pole in the noise gain at about 3.2 kHz, but the op-amp's open-loop response crosses noise gain near 500 kHz — guaranteeing oscillation or severe ringing. Add Cf = 0.3 pF across Rf: this puts a zero at ~530 kHz, right at the crossover. The phase margin jumps from near-zero to 45°+, and the step response settles cleanly.

Rule of thumb for TIAs: Cf ≈ √(Cin / (2π · Rf · GBW)), where GBW is the op-amp's gain-bandwidth product. For our example: √(50pF / (2π · 1MΩ · 10MHz)) ≈ 0.28 pF. Use a real capacitor here — PCB trace coupling alone can give you 0.1–0.3 pF of stray, so sometimes the trace geometry is your compensation.

Watch out: A zero you add for stability also limits your signal bandwidth — the closed-loop response rolls off at fzero. Lead compensation buys phase margin and determines your usable bandwidth, so the placement is a hard tradeoff, not free.

See it in action: Check out Without Flux There Would be No Good Solder Connection! by Circuit Specialists to see this theory applied.
Key Takeaway: Lead compensation cancels a troublesome pole with a deliberately-placed zero, reclaiming the bandwidth that dominant-pole compensation would have thrown away.

All newsletters