A programmable delay line is a chain of buffer stages whose total propagation delay you can adjust at runtime, usually by selecting a tap point along the chain or by tuning the drive strength of each stage. It's the hardware equivalent of nudging a signal a few picoseconds earlier or later — no PLL, no clock generation, just a controllable amount of "wire time" added to a path.

The simplest topology is a tapped inverter chain: N inverter pairs in series, with a mux selecting which tap feeds the output. If each inverter pair costs 40 ps, a 64-tap chain gives you 0 to 2.56 ns of delay in 40 ps steps. Finer resolution comes from current-starved inverters, where a control voltage or DAC throttles the tail current — starve the inverter and it charges its load slower, adding delay smoothly down to sub-picosecond granularity.

The hard part is PVT stability. An inverter delay swings 2-3× across process, voltage, and temperature corners, so an open-loop delay line calibrated at 25°C is useless at 85°C. The fix is a DLL-referenced delay line: build a replica chain, lock it to a known clock period using a phase detector, and reuse the same bias voltage on your working chain. Now each tap represents a fixed fraction of the reference period, not a fixed number of picoseconds — which is usually what you actually want.

Real-world example: DDR4 write leveling. When the memory controller sends DQS (data strobe) alongside DQ (data), each DRAM chip on the DIMM sits at a slightly different distance from the controller — fly-by topology means chip 0 sees the strobe 400 ps before chip 7. Each DRAM has a per-byte-lane programmable delay line the controller trains during initialization: the controller sweeps the DQS delay in ~10 ps steps while sampling a known pattern, finds the edge of the valid window, and locks the delay at the center. Every subsequent write uses that calibrated delay so DQS arrives centered in the DQ eye at every chip.

Rule of thumb: for a delay line meant to align to a clock, size the total delay range to at least 1.5× the clock period and the step size to ≤ 1/20 of the unit interval. Less range and you can't cover the full alignment window across corners; coarser steps and you leave more than 5% of the eye on the table during calibration.

Programmable delays also show up in hold-time fixing during place-and-route (drop in a delay buffer to push a fast path later), SerDes CDR (fine-tuning sample position within the bit period), and time-to-digital converters (the tap position at the moment of a stop pulse encodes elapsed time).