An SRAM read works by tipping a differential bit-line pair one way or the other. But before the cell can tip anything, both bit-lines must start from a known, identical voltage. That's what precharge and equalization do — and getting them wrong makes your SRAM either slow, unreliable, or destructive to the cell contents.

The problem. A 6T SRAM cell drives one of the bit-lines low through a pass transistor when the word-line rises. The sense amplifier detects which side went down. But bit-lines are long — hundreds of cells hang off each one, giving 100–500 fF of capacitance. If the two bit-lines start at different voltages (from the previous read, or from leakage drift), the sense amp can't tell the difference between "the cell drove one side down" and "the lines were already unequal." You get a wrong read.

The circuit. Three PMOS transistors sit at the top of every column: two pull-ups from VDD to BL and BLB, and one equalizer shorting BL to BLB. All three share a gate signal, PCH_n, which goes low during the idle phase of the clock. The pull-ups charge both lines toward VDD; the equalizer forces them to exactly the same voltage, killing any residual imbalance from the previous cycle. When PCH_n rises, the lines float at VDD (or half-VDD, in low-swing designs) and the word-line is safe to fire.

Half-VDD precharge. Fast SRAMs precharge to VDD/2 instead of VDD. Why? The cell only needs to develop ~50–100 mV of differential for the sense amp to latch. Starting at VDD/2 means the cell pulls one side down by 50 mV instead of pulling from VDD down by 50 mV — same signal, but the bit-line swing after sensing is smaller, saving CV² switching energy on the massive bit-line capacitance. A 512-row column swinging 300 mV instead of 900 mV saves ~89% of the read energy on that column.

Rule of thumb. Precharge time ≈ 3 × R_PMOS × C_BL. For a 200 fF bit-line and a 5 kΩ pull-up, that's 3 ns — often the dominant slice of the SRAM cycle time. Wider PMOS shortens it but costs area on every column.

Real-world example. Intel's L1 caches use hierarchical bit-lines: local bit-lines span 16 cells and precharge in ~100 ps, then a local sense amp drives a global bit-line that spans the rest of the column. This breaks the CV product into two smaller CVs and lets the cache run at 4+ GHz.