You use RAM every day, but there are two fundamentally different transistor-level designs hiding behind that term. Understanding them explains why your CPU has cache (SRAM) and main memory (DRAM), and why they behave so differently.

SRAM: The Six-Transistor Cell

An SRAM cell uses six transistors arranged as two cross-coupled inverters with two access transistors. Each inverter's output feeds the other's input, forming a bistable loop — it holds a 0 or 1 indefinitely as long as power is on. The two access transistors connect the cell to a pair of complementary bitlines when the wordline goes high.

• Read: Precharge both bitlines high. Assert the wordline. The side storing 0 pulls its bitline slightly lower. A sense amplifier detects the difference.
• Write: Drive the bitlines to complementary values (one high, one low). Assert the wordline. The strong external drivers overpower the weak internal inverters, forcing the cell to flip.
• No refresh needed. The cross-coupled loop is self-sustaining.

DRAM: The One-Transistor Cell

A DRAM cell is breathtakingly simple: one transistor and one tiny capacitor. The bit is stored as charge on the capacitor. The transistor acts as a gate between the capacitor and the bitline.

• Read: Precharge the bitline to ½V_DD. Assert the wordline. Charge sharing between the capacitor and the much-larger bitline capacitance nudges the bitline voltage slightly up or down. A sense amplifier detects this — typically a 100-200mV swing on a ~1V signal.
• Write: The sense amplifier drives the bitline to full 0 or V_DD, and the transistor writes it back to the capacitor.
• Destructive read. Reading drains the capacitor, so every read must be followed by a write-back.
• Refresh required. Capacitor leakage drains charge in ~64ms, so every row must be periodically re-read and rewritten.

The Engineering Tradeoff

SRAM uses 6 transistors per bit. DRAM uses 1 transistor + 1 capacitor. That's roughly a 6× density advantage for DRAM. A modern DRAM chip stores 16 Gbit on a single die; an equivalent SRAM would need approximately 6× the silicon area, making it economically absurd for main memory.

But SRAM is fast. No precharge-sense-restore cycle, no refresh overhead. Typical SRAM access: 1-2ns. Typical DRAM access: 50-70ns once you account for row activation, column access, and precharge. That 30-50× speed gap is exactly why your CPU has a hierarchy: small, fast SRAM caches close to the core, backed by large, dense, slower DRAM.

Rule of thumb: Every doubling of cache size adds roughly 1-2 cycles of access latency, which is why L1 is 32-64KB (3-4 cycles), L2 is 256KB-1MB (~12 cycles), and L3 is several MB (~40 cycles). Beyond that, you hit DRAM.