Modern CPUs can burn over 250W — enough to run a heat lamp. Without aggressive power management hardware, they'd either throttle constantly or literally destroy themselves. Power management isn't a software afterthought; it's deeply wired into the silicon.

The physics you need to know: Dynamic power in CMOS follows the equation P = α × C × V² × f, where α is the activity factor (how often transistors switch), C is capacitance, V is voltage, and f is frequency. That V² term is the key insight — cutting voltage by half cuts dynamic power to one quarter. This is why voltage scaling is the single most effective lever.

DVFS (Dynamic Voltage and Frequency Scaling) exploits this relationship. The CPU defines discrete operating points (called P-states in ACPI) that pair a voltage with a frequency. An Intel Core i9-13900K, for example, can drop from its 5.8 GHz turbo at ~1.4V down to 800 MHz at ~0.65V during idle. The power difference is enormous: roughly a 20× reduction. The hardware voltage regulator (VRM) on the motherboard physically adjusts the supply rail, and the CPU's PLL relocks to the new frequency. Transitions take on the order of 10–100 microseconds — fast enough to respond to workload changes multiple times per second, but slow enough that you don't want to thrash between states.

Clock gating operates at a finer granularity. Instead of changing the global clock, the hardware inserts AND gates on the clock signal to individual functional units. When the FPU has no work, its clock tree is gated off — the transistors stop switching entirely, driving α to zero for that block. This is invisible to software and happens cycle-by-cycle. Modern designs gate at hundreds of independent domains. ARM's big.LITTLE documentation notes that clock gating alone can save 20-40% of dynamic power in typical mobile workloads.

Power gating goes further by cutting the supply voltage to entire blocks using high-Vt sleep transistors, eliminating static (leakage) power too. This matters because at modern process nodes (5nm and below), leakage can account for 30-50% of total power. The tradeoff: power gating takes microseconds to wake up because you must restore state and recharge capacitances, so it's used for coarser-grained sleep (C-states like C6, where register contents are flushed to cache).

Rule of thumb: Each voltage reduction of 10% yields roughly a 19% dynamic power reduction (since 0.9² = 0.81). This is why undervolting is so popular among enthusiasts — even modest voltage drops yield significant thermal and power savings, until you hit stability limits.

In practice, these mechanisms are orchestrated by a dedicated microcontroller on-die. Intel calls theirs the Power Control Unit (PCU); AMD uses the System Management Unit (SMU). These run firmware that monitors temperature sensors, current draw, and workload hints to make millisecond-level decisions about P-states, clock gating domains, and which cores to power gate — all without OS intervention.