A convolutional encoder is a shift register that XORs its taps to produce two output bits for every input bit — cheap to build, but it spreads each bit's influence across many outputs. To decode it, you can't just look at one received bit; you have to find the most likely input sequence that could have produced the noisy bits you observed. That's what a Viterbi decoder does, and it does it in silicon at hundreds of megabits per second.

The trick is the trellis: a graph where each node is an encoder state at a given time step. For a rate-1/2, constraint-length K=7 encoder (the NASA standard, also used in 802.11a/g), there are 2^(K-1) = 64 states. Each state has exactly two incoming edges (from the two possible previous input bits) and two outgoing edges. The decoder's job is to find the single path through the trellis with the smallest accumulated error.

The workhorse block is the ACS unit — Add, Compare, Select. For each state at time t:

• Add the branch metric (Hamming distance for hard decisions, Euclidean for soft) to each of the two incoming path metrics.
• Compare the two sums.
• Select the smaller one as the new path metric, and record which predecessor won in a survivor bit.

For 64 states, you need 64 ACS units running in parallel every cycle. This is the critical path — path metrics feed back on themselves, so you can't just pipeline your way out. Modern designs use modulo arithmetic on the metrics to prevent overflow without periodic renormalization stalls.

After ACS, you need to trace back through the survivor memory to recover the actual decoded bits. Rule of thumb: traceback depth ≈ 5×K gives you within 0.1 dB of infinite-depth performance. So K=7 needs about 35 stages of survivor history. Two common architectures: register-exchange (fast but power-hungry — shift the entire survivor path every cycle) and traceback RAM (slower but denser — write survivors to memory, then walk backward on demand).

Real-world example: An 802.11a receiver at 54 Mbps needs to decode 27 Msymbols/sec of coded bits. At 64 states with two ACS ops per state per symbol, that's 3.5 billion ACS operations per second — trivially met by a 200 MHz clock with parallel ACS units, but a nightmare to code in software.

Once you go past K=9, the state count explodes (256+) and Viterbi becomes uneconomical — that's where LDPC and turbo codes took over for modern 4G/5G.