You already know ARM and x86 differ in their ISA philosophies. RISC-V is what happens when academics in 2010 asked: "If we designed an ISA today, with zero legacy baggage, what would we do differently?" The answer is surprisingly opinionated.

The modular base-plus-extensions model. RISC-V's most radical decision is that the ISA isn't monolithic. There's a tiny frozen base — RV32I has just 47 instructions — and everything else is an optional extension. Multiply/divide (M), atomics (A), floating-point (F/D), compressed instructions (C), vector (V). A microcontroller for a sensor node implements RV32I+M and nothing else. A Linux-capable application processor implements RV64GC (shorthand for IMAFDC). This means the same ISA specification spans a $0.10 embedded core to a server chip, without either paying for the other's complexity.

Encoding regularity that hardware designers love. In x86, instructions range from 1 to 15 bytes, and the decoder is one of the most power-hungry parts of the chip. RISC-V base instructions are fixed 32-bit, with source registers always at bits 19:15 and 24:20, and the destination at 11:7 — regardless of instruction type. This means the register file can begin its read before the instruction is fully decoded. The C extension adds 16-bit compressed instructions, but even these decompose 1:1 into base instructions, so they're handled by a simple pre-decoder, not a complex decode stage.

No condition codes. ARM and x86 use flags registers (carry, zero, overflow) set as side effects. RISC-V eliminates them entirely. Branches compare two registers directly: BLT x5, x6, offset. This removes a class of data hazards — in a superscalar pipeline, flag-setting instructions create false dependencies between otherwise independent operations. RISC-V trades a slightly wider branch instruction for cleaner out-of-order scheduling.

Real-world example: SiFive U74. This is a 64-bit, dual-issue, in-order RISC-V core used in the StarFive VisionFive 2 board. Its decode stage is remarkably small — roughly 15–20% the transistor count of a comparable x86 decoder — because the encoding is so regular. That saved area goes toward a larger L1 cache and a wider issue path.

A useful rule of thumb: decoder complexity scales roughly with N × log₂(L), where N is the number of distinct instruction formats and L is the maximum instruction length in bytes. x86 has ~15 formats and L=15, giving ~58. RISC-V base has 6 formats and L=4, giving ~12. That's nearly a 5× reduction in decode complexity, which directly translates to power savings — critical in mobile and embedded.

The tradeoff. Code density. Fixed-width 32-bit encoding wastes bits. RISC-V binaries are typically 10–20% larger than ARM A64 and 20–30% larger than x86-64 for the same program. The C extension claws back most of that gap (bringing it within 5% of ARM), but it adds decode complexity — the very thing RISC-V tried to avoid. Nothing is free.